9DBU0931 Datasheet, PDF (2/17 Pages) Integrated Circuit Systems – slew rate for each output

9DBU0931 DATASHEET
Pin Configuration
48 47 46 45 44 43 42 41 40 39 38 37
vSADR_tri 1
36 DIF5#
vOE8# 2
35 DIF5
DIF8 3
34 vOE4#
DIF8# 4
33 DIF4#
VDDR1.5 5
CLK_IN 6
9DBU0931
32 DIF4
31 VDDIO
CLK_IN# 7
GNDR 8
epad is GND
30 VDDA1.5
29 GNDA
GNDDIG 9
28 vOE3#
SCLK_3.3 10
27 DIF3#
SDATA_3.3 11
26 DIF3
VDDDIG1.5 12
25 vOE2#
13 14 15 16 17 18 19 20 21 22 23 24
48-pin VFQFPN, 6x6 mm, 0.4mm pitch
^v prefix indicates internal 120KOhm pull up AND
pull down resistor (biased to VDD/2)
v prefix indicates internal 120KOhm pull down resisto
^ prefix indicates internal 120KOhm pull up resistor
SMBus Address Selection Table
State of SADR on first application of
CKPWRGD_PD#
SADR
0
M
1
Address
1101011
1101100
1101101
+ Read/Write bit
x
x
x
Power Management Table
CKPWRGD_PD#
0
1
1
1
CLK_IN
X
Running
Running
Running
SMBus
OEx bit
X
0
1
1
OEx# Pin
X
X
0
1
DIFx
True O/P Comp. O/P
Low
Low
Low
Low
Running
Running
Low
Low
Power Connections
VDD
5
12
Pin Number
VDDIO
GND
8
9
Description
Input
receiver
analog
Digital Power
20,30,31,38 13,21,31,39,47 22,29,40 DIF outputs
Note: epad on this device is not electrically connected to the die.
It should be connected to ground for best thermal performance.
9 O/P 1.5V PCIE GEN1-2-3 FAN-OUT BUFFER
2
REVISION C 04/22/15