9DBU0741 Datasheet, PDF (3/17 Pages) Integrated Circuit Systems – slew rate for each output

9DBU0741 DATASHEET
Pin Descriptions
PIN #
PIN NAME
1 vSADR_tri
2 vOE6#
3 DIF6
4 DIF6#
5 VDDR1.5
6 CLK_IN
7 CLK_IN#
8 GNDDIG
9 SCLK_3.3
10 SDATA_3.3
11 VDDDIG1.5
12 VDDIO
13 vOE0#
14 DIF0
15 DIF0#
16 VDD1.5
17 VDDIO
18 DIF1
19 DIF1#
20 NC
21 vOE1#
22 DIF2
23 DIF2#
24 vOE2#
25 VDDA1.5
26 VDDIO
27 DIF3
28 DIF3#
29 vOE3#
30 NC
31 VDD1.5
32 VDDIO
33 DIF4
34 DIF4#
35 vOE4#
36 DIF5
37 DIF5#
38 vOE5#
39 VDDIO
40 ^CKPWRGD_PD#
41 ePAD
PIN
TYPE
DESCRIPTION
LATCHE Tri-level latch to select SMBus Address. See SMBus Address Selection Table.
D IN
IN ^{Active low input for enabling DIF pair 6. This pin has an internal pull-down.}
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
PWR ^{1.5V power for differential input clock (receiver). This VDD should be treated as an}
Analog power rail and filtered appropriately.
IN True Input for differential reference clock.
IN Complementary Input for differential reference clock.
GND Ground pin for digital circuitry
IN Clock pin of SMBus circuitry, 3.3V tolerant.
I/O Data pin for SMBus circuitry, 3.3V tolerant.
PWR 1.5V digital power (dirty power)
PWR Power supply for differential outputs
IN ^{Active low input for enabling DIF pair 0. This pin has an internal pull-down.}
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
PWR Power supply, nominally 1.5V
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
N/A No Connection.
IN ^{Active low input for enabling DIF pair 1. This pin has an internal pull-down.}
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN ^{Active low input for enabling DIF pair 2. This pin has an internal pull-down.}
1 =disable outputs, 0 = enable outputs
PWR 1.5V power for the PLL core.
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN ^{Active low input for enabling DIF pair 3. This pin has an internal pull-down.}
1 =disable outputs, 0 = enable outputs
N/A No Connection.
PWR Power supply, nominally 1.5V
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN ^{Active low input for enabling DIF pair 4. This pin has an internal pull-down.}
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN ^{Active low input for enabling DIF pair 5. This pin has an internal pull-down.}
1 =disable outputs, 0 = enable outputs
PWR Power supply for differential outputs
Input notifies device to sample latched inputs and start up on first high assertion. Low
IN enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin
has internal pull-up resistor.
GND Connect paddle to ground.
REVISION C 04/22/15
3
7 O/P 1.5V PCIE GEN1-2-3 FAN-OUT BUFFER W/ZO=100OHMS