9DB233 Datasheet, PDF (3/17 Pages) Integrated Device Technology – Two Output Differential Buffer for PCIe Gen3

9DB233
TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3
Pin Descriptions
PIN
PIN # _NAME
1 PLL_BW
2 SRC_IN
3 SRC_IN#
PIN TYPE
IN
IN
IN
DESCRIPTION
3.3V input for selecting PLL Band Width
0 = low, 1= high
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
4 vOE0# IN
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
5 VDD
PWR
6 GND
PWR
7 DIF_0 OUT
8 DIF_0# OUT
9 VDD
PWR
10 SMBDAT I/O
11 SMBCLK IN
12 VDD
PWR
13 DIF_1# OUT
14 DIF_1 OUT
15 GND
PWR
16 VDD
PWR
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Data pin of SMBUS circuitry, 5V tolerant
Clock pin of SMBUS circuitry, 5V tolerant
Power supply, nominal 3.3V
0.7V differential Complementary clock output
0.7V differential true clock output
Ground pin.
Power supply, nominal 3.3V
17 vOE1# IN
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
18 IREF
OUT
19 GNDA
20 VDDA
PWR
PWR
This pin establishes the reference for the differential current-mode output
pairs. It requires a fixed precision resistor to ground. 475ohm is the standard
value for 100ohm differential impedance. Other impedances require
different values. See data sheet.
Ground pin for the PLL core.
3.3V power for the PLL core.
Note:
Pins preceeded by ' v ' have internal 120K ohm pull down resistors
IDT® TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3
3
9DB233
REV E 021914