ICS954119 Datasheet, PDF (2/17 Pages) Integrated Circuit Systems – Programmable Timing Control Hub™ for Next Gen P4™ processor

Integrated
Circuit
Systems, Inc.
ICS954119
Advance Information
Pin Description
PIN # PIN NAME
1 GND
2 PCICLK3
3 PCICLK4
4 PCICLK5
5 GND
6 VDDPCI
7 PCICLK_F0
8 FSLA/PCICLK_F1
9 FSLB/PCICLK_F2
10 VDD48
11 **SEL24_48#/24_48MHz
12 USB_48MHz
13 GND
14 DOTT_ 96MHz
15 DOTC_96MHz
16 Vtt_PwrGd#/PD
17 PCIEXT0
18 PCIEXC0
19 VDDPCIEX
20 GND
21 PCIEXT1
22 PCIEXC1
23 PCIEXT2
24 PCIEXC2
25 GND
26 SRCCLKT
27 SRCCLKC
28 VDDSRC
PIN
TYPE
PWR
OUT
OUT
OUT
PWR
PWR
OUT
I/O
I/O
PWR
I/O
OUT
PWR
OUT
OUT
IN
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
OUT
OUT
PWR
DESCRIPTION
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin.
Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP# .
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / 3.3V PCI free running clock
output.
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values./ 3.3V PCI free running clock
output.
Power pin for the 48MHz output.3.3V
Latched select input for 24/48MHz output / 24/48MHz clock output.
1=24MHz, 0 = 48MHz.
48.00MHz USB clock
Ground pin.
True clock of differential pair for 96.00MHz DOT clock.
Complement clock of differential pair for 96.00MHz DOT clock.
Vtt_PwrGd# is an active low input used to determine when latched inputs
are ready to be sampled. PD is an asynchronous active high input pin
used to put the device into a low power state. The internal clocks, PLLs
and the crystal oscillator are stopped.
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
Power supply for PCI Express clocks, nominal 3.3V
Ground pin.
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
Ground pin.
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
Supply for SRC clocks, 3.3V nominal
0875—05/24/04
2