ICS952301 Datasheet, PDF (2/12 Pages) Integrated Circuit Systems – Frequency Timing Generator for Transmeta Systems

ICS952301
Advance Information
Pin Descriptions
PIN # PIN
1 GNDREF
2 X1
3 X2
4 PD#
5 PCICLK0
6 PCICLK1
7 GNDPCI
8 VDDPCI
9 PCICLK21
10 PCICLK3
11 PCICLK41
12 GNDPCI
13 VDDPCI
14 PCICLK5
15 PCICLK6
16 SDATA
17
24-48MHz/Sel
48_24#*
18 48MHz
19 GND48
20 VDD48
21 SCLK
22 PCI_STOP#
23 CPUCLK0
24 GNDCPU/CORE
25 VDDCPU/CORE
26 CPU_STOP#
REF/ 1X or 2X
27 _{Programmable*}
28 VDDREF
PIN
TYPE
PWR
IN
OUT
IN
OUT
OUT
PWR
PWR
OUT
OUT
OUT
PWR
PWR
OUT
OUT
I/O
DESCRIPTION
Ground pin.
Crystal input, nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Asynchronous active low input pin used to power down the
device into a low power state. The internal clocks are
disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 3ms.
PCI clock outputs.
PCI clock outputs.
Ground pin.
Supply for PCI, nominal 3.3V.
PCI clock outputs.
PCI clock outputs.
PCI clock outputs.
Ground pin.
Supply for PCI, nominal 3.3V.
PCI clock outputs.
PCI clock outputs.
Data pin for I²C circuitry 5V tolerant
I/O
Selectable 48 or 24MHz output
OUT
PWR
PWR
IN
IN
OUT
PWR
PWR
IN
OUT
PWR
48MHz output clock
Ground pin.
Power for 24 & 48MHz output buffers and fixed PLL core.
Clock pin of I²C circuitry 5V tolerant
Stops all PCICLKs besides the PCICLK_F clocks at logic 0
level, when input low
CPU clock outputs.
Ground pin.
3.3V power for the PLL core.
Stops all CPUCLKs besides the CPUCLK_F clocks at logic 0
level, when input low
14.318 MHz reference clock. Latched input select for strength
of PCICLK(4,2). Default 1X with internal pullup.
3.3V power for the REF.
0673—07/09/02
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