ICS94211 Datasheet, PDF (2/16 Pages) Integrated Circuit Systems – Programmable System Frequency Generator for PII/III™

ICS94211
General Description
The ICS94211 is a single chip clock solution for desktop designs using the BX/Apollo Pro133/ALI 1631 style chipset. It provides all
necessary clock signals for such a system.
The ICS94211 belongs to ICS new generation of programmable system clock generators. It employs serial programming I²C interface
as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew,
changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks. This device also has ICS
propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system become unstable from over
clocking.
Pin Configuration
PIN NUMBER
1
2
3, 9, 16, 22,
33, 39, 45
4
PIN NAME
VDDREF
REF0
PCI_STOP#¹
GND
X1
5
6, 14
7
8
X2
VDDPCI
PCICLK_F
MODE^{1, 2}
FS3
PCICLK0
13, 12, 11, 10 PCICLK (4:1)
15
BUFFER IN
17, 18, 20, 21, 28, 29,
31, 32, 34, 35, 37, 38, SDRAM (12:0)
40
19, 30, 36
VDDSDR
23
SDATA
24
SCLK
24MHz
25
FS1^{1, 2}
48MHz
26
FS0^{1, 2}
27
VDD48
41
RESET
42
VDDLCPU
43
CPUCLK1
44
CPUCLK0
REF1
46
FS2^{1, 2}
47
IOAPIC
48
VDDL
TYPE
PWR
OUT
IN
DESCRIPTION
Ref, XTAL power supply, nominal 3.3V
14.318 Mhz reference clock.
Halts PCICLK(0:4) clocks at logic 0 level, when input low (In mobile
mode, MODE=0)
PWR Ground
IN
OUT
PWR
OUT
IN
IN
OUT
OUT
IN
Crystal input, has internal load cap (36pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (36pF)
Supply for PCICLK_F and PCICLK (0:4), nominal 3.3V
Free running PCI clock not affected by PCI_STOP# for power management.
Pin 7 function select pin, 1=Desktop Mode, 0=Mobile Mode. Latched Input.
Frequency select pin. Latched Input. Internal Pull-down to GND
PCI clock outputs. Syncheronous to CPU clocks with 1-48ns skew
(CPU early)
PCI clock outputs. Syncheronous to CPU clocks with 1-48ns skew
(CPU early)
Input to Fanout Buffers for SDRAM outputs.
OUT
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset)
PWR
I/O
IN
OUT
IN
OUT
IN
PWR
OUT
PWR
OUT
OUT
OUT
IN
OUT
PWR
Supply for SDRAM (0:12) and CPU PLL Core, nominal 3.3V.
Data input for I²C serial input, 5V tolerant input
Clock input of I²C input, 5V tolerant input
24MHz output clock
Frequency select pin. Latched Input.
48MHz output clock
Frequency select pin. Latched Input
Power for 24 & 48MHz output buffers and fixed PLL core.
Real time system reset signal for frequency ratio change or watchdog
timmer timeout. This signal is active low.
Supply for CPU clocks, either 2.5V or 3.3V nominal
CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low
Free running CPU clock. Not affected by the CPU_STOP#
14.318 MHz reference clock.
Frequency select pin. Latched Input
IOAPIC clock output. 14.318 MHz Powered by VDDL.
Supply for IOAPIC, either 2.5 or 3.3V nominal
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
2