ICS94211 Datasheet, PDF (10/16 Pages) Integrated Circuit Systems – Programmable System Frequency Generator for PII/III™

ICS94211
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V_DD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = 0 - 70C; Supply Voltage V_DD = 3.3 V +/-5%, V_DDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
MIN TYP
MAX UNITS
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Operating Supply
Current
V_IH
V_IL
I_IH
I_IL1
I_IL2
I_DD3.3OP
V_IN = V_DD
V_IN = 0 V; Inputs with no pull-up resistors
V_IN = 0 V; Inputs with pull-up resistors
C_L = max cap loads;
CPU=66-133 MHz, SDRAM=100 MHz
CPU=133 MHz, SDRAM=133 MHz
2
V_SS-0.3
-5
-5
-200
V_DD+0.3
V
0.8
V
5
µ^A
µ^A
124
350
135
500
mA
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance¹
Transition time¹
Settling time¹
Clk Stabilization¹
Delay¹
Skew¹
I_DD2.5OP
I_DD3.3PD
F_i
L_pin
C_IN
C_OUT
C_INX
T_trans
T_s
T_STAB
t_PZH,t_PZL
t_PHZ,t_PLZ
tcpu-pci
C_L = max cap loads;
C_L = 0 pF; Input address to VDD or GND
V_DD = 3.3 V
Logic Inputs
Output pin capacitance
X1 & X2 pins
To 1st crossing of target frequency
From 1st crossing to 1% target frequency
From V_DD = 3.3 V to 1% target frequency
Output enable delay (all outputs)
Output disable delay (all outputs)
V_T = 1.5V; VTL=1.25V
18
70
600
14.318
7
5
6
27
45
3
3
3
1
10
1
10
2.45
4
µ^A
MHz
nH
pF
pF
pF
ms
ms
ms
ns
ns
ns
1_{Guaranteed by design, not 100% tested in production.}
10