ICS93V857YL-025T Datasheet, PDF (2/10 Pages) Integrated Circuit Systems – 2.5V Wide Range Frequency Clock Driver

ICS93V8 5 7 - X X X
Pin Descriptions
PIN NUMBER
PIN NAME
4, 11, 12, 15, 21,
28, 34, 38, 45,
VDD
1, 7, 8, 18, 24, 25,
31, 41, 42, 48
GND
16
AVDD
17
AGND
27, 29, 39, 44, 46,
22, 20, 10, 5, 3
CLKT(9:0)
26, 30, 40, 43, 47,
23, 19, 9, 6, 2
CLKC(9:0)
14
CLK_INC
13
CLK_INT
33
FB_OUTC
32
FB_OUTT
36
FB_INT
35
FB_INC
37
PD#
TYPE
PWR Power supply 2.5V
DESCRIPTION
PWR Ground
PWR Analog power supply, 2.5V
PWR Analog ground.
OUT "True" Clock of differential pair outputs.
OUT "Complementary" clocks of differential pair outputs.
IN
IN
OUT
OUT
IN
IN
IN
"Complementary" reference clock input
"True" reference clock input
"Complementary" Feedback output, dedicated for external feedback. It
switches at the same frequency as the CLK. This output must be wired
to FB_INC.
"True" " Feedback output, dedicated for external feedback. It switches
at the same frequency as the CLK. This output must be wired to
FB_INT.
"True" Feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error.
"Complementary" Feedback input, provides signal to the internal PLL
for synchronization with CLK_INC to eliminate phase error.
Power Down. LVCMOS input
This PLL Clock Buffer is designed for a V_DD of 2.5V, AV_DD of 2.5V and differential data input and output levels.
ICS93V857-XXX is a zero delay buffer that distributes a differential clock input pair (CLK_INC, CLK_INT) to ten
differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock output (FB_OUT,
FB_OUTC). The clock outputs are controlled by the input clocks (CLK_INC, CLK_INT), the feedback clocks (FB_INT,
FB_INC), the 2.5-V LVCMOS input (PD#) and the Analog Power input (AV_DD). When input (PD#) is low while power is
applied, the receivers are disabled, the PLL is turned off and the differential clock outputs are Tri-Stated. When AV_DD
is grounded, the PLL is turned off and bypassed for test purposes.
When the input frequency is less than the operating frequency of the PLL, appproximately 20MHz, the device will enter
a low power mode. An input frequency detection circuit on the differential inputs, independent from the input buffers,
will detect the low frequency condition and perform the same low power features as when the (PD#) input is low.When
the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on, the inputs and
outputs will be enabled and PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input
clock pair (CLK_INC, CLK_INT).
The PLL in ICS93V857-XXX clock driver uses the input clocks (CLK_INC, CLK_INT) and the feedback clocks (FB_INT,
FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT [0:9], CLKC [0:9]).
ICS93V857-XXX is also able to track Spread Spectrum Clock (SSC) for reduced EMI.
ICS93V857-XXX is characterized for operation from 0°C to 85°C.
0693K—03/13/03
2