ICS9250-11 Datasheet, PDF (2/8 Pages) Integrated Circuit Systems – Frequency Timing Generator for PENTIUM II/III Systems

ICS9250-11
Pin Descriptions
Pin number
1, 52, 53
Pin name
GNDLAPIC
2, 3, 50, 51, 54, 55 IOAPIC (0:5)
4, 49, 56
5, 11
6
7
VDDLAPIC
VDDREF
X1
X2
REF0
9
FREQ_APIC#
REF1
10
TEST#
12, 19
VDD66
13, 14, 17, 18 3V66[0:3]
8, 15, 16, 23, 24
21, 22
25
26
27
28
GND
3V33MHz
VDDCOR
GND48
48MHz
VDD48
29
SEL 133/100#
30, 31
SEL[0:1]
32
SPREAD#
33
VDDLCPU/2
34, 35
CPU/2[0:1]
36
37, 44, 45
38, 39, 42, 43, 46,
47
40, 41, 48
GNDLCPU/2
GNDLCPU
CPUCLK[0:5]
VDDLCPU
Type
PWR
OUT
PWR
PWR
IN
OUT
OUT
OUT
OUT
OUT
PWR
OUT
PWR
OUT
PWR
PWR
OUT
PWR
IN
IN
IN
PWR
OUT
PWR
PWR
OUT
PWR
Description
Ground pin for the IOAPIC outputs.
2.5V clock outputs running divide synchronous with the CPU
(Host bus) clock frequency. The default APIC is running at ¼ of
CPUCLK frequency.
When FREQ_APIC is strapped low, the APIC is running at fixed
16.67 MHz.
If CPU = 133 MHz, APIC = CPU/8
If CPU = 100 MHz, APIC = CPU/6
Power pin for the IOAPIC outputs. 2.5V.
Power pin for REF clocks
XTAL_IN 14.318MHz crystal input
XTAL_OUT Crystal output
3.3V 14.318 MHz clock output. APIC clock strapping option for
fixed 16.67 MHz APIC clock outputs.
If FREQ_APIC# = 0, APIC Clock = 16.67 MHz
If FREQ_APIC# = Open, APIC Clock = CPU/4
3.3V 14.318MHz clock output.
TEST# is sampled low (external with 10k pulldown). All clock
outputs are Tri-State.
power pin for the 3V66 clocks.
66MHz outputs at 3.3V. These outputs are stopped when
CPU_STOP# is driven active..
Ground pin for 3V outputs.
3.3V Fixed 33MHz clock output.
3.3V power for PLL core.
Ground pin for the 48MHz output
Fixed 48MHz clock output. 3.3V
Power pin for the 48MHz output.
This selects the frequency for the CPU and CPU/2 outputs. High =
133MHz, Low=100MHz
Function select pins. See truth table for details.
Enables spread spectrum when active(Low). modulates all the CPU,
PCI, IOAPIC, 3V66 and CPU/2 clocks. Does not affect the REF and
48MHz clocks. 0.5% down spread modulation.
Power pin for the CPU/2 clocks. 2.5V
2.5V clock outputs at 1/2 CPU frequency. 66MHz or50MHz
depending on the state of the SEL 133/100# input pin.
Ground pin for the CPU/2 clocks.
Ground pin for the CPUCLKs
Host bus clock output at 2.5V. 133MHz or 100MHz depending on
the state of the SEL 133/100MHz.
Power pin for the CPUCLKs. 2.5V
2