ICS9248-97 Datasheet, PDF (2/14 Pages) Integrated Circuit Systems – Frequency Timing Generator for PENTIUM II Systems

ICS9248-97
General Description
The ICS9248-97 is a main clock synthesizer chip for Pentium II based systems using Rambus Interface DRAMs. This chip
provides all the clocks required for such a system when used with a Direct Rambus Clock Generator(DRCG) chip such as the
ICS9212-01.
Spread Spectrum may be enabled by driving the SPREAD# pin active. Spread spectrum typically reduces system EMI by 8dB
to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-97
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
The CPU/2 clocks are inputs to the DRCG.
Pin Descriptions
Pin number
Pin name
1, 7, 13, 19, 25, 31 GND
2
REF0
REF1
3
SEL24_48
4, 10, 16, 23, _VDD
28, 35
5
X1
6
X2
PCICLK_F
8
FS0
9
PCICLK0
FS1
PCICLK1
11
FS2
PCICLK2
12
FS3
22, 21, 20, 18, 17, _{PCICLK (9:3)}
15, 14
24
PD#
26
27
29
30
32, 33, 34
36
37, 38, 40
39
41
42
43
45
44, 46, 47
48
24_48MHz
48MHz
FS4
SCLK
SDATA
3V66 (2:0)
GNDLCPU
CPUCLK (2:0)
VDDLCPU
GNDLCPU/2
CPU/2
VDDLCPU/2
GNDLAPIC
IOAPIC (2:0)
VDDLAPIC
Type
PWR
OUT
OUT
IN
Description
Ground pins
14.318MHz reference clock outputs at 3.3V
14.318MHz reference clock outputs at 3.3V
Logic input to select 24 or 48MHz for pin 26 output
PWR Power pins 3.3V
IN
OUT
OUT
IN
OUT
IN
OUT
IN
OUT
IN
XTAL_IN 14.318MHz crystal input
XTAL_OUT Crystal output
Free running PCI clock at 3.3V. Synchronous to CPU clocks. Not
affected by the PCI_STOP# input.
Logic - input for frequency selection
PCI clock output at 3.3V. Synchronous to CPU clocks.
Logic - input for frequency selection
PCI clock output at 3.3V. Synchronous to CPU clocks.
Logic - input for frequency selection
PCI clock output at 3.3V. Synchronous to CPU clocks.
Logic - input for frequency selection
OUT PCI clock outputs at 3.3V. Synchronous to CPU clocks.
IN
OUT
OUT/IN
IN
IN
IN
OUT
PWR
OUT
PWR
PWR
OUT
PWR
PWR
OUT
PWR
This asynchronous input powers down the chip when drive
active(Low). The internal PLLs are disabled and all the output clocks
are held at a Low state.
24 or 48MHz output selectable by
SEL24_48# (0=48MHz 1=24MHz)
Fixed 48MHz clock output. 3.3V
Logic - input for frequency selection
Clock input of I²C input
Data input for I²C serial input.
3.3V clock outputs. These outputs are stopped when CPU_STOP#
is driven active..
Ground pin for the CPUCLKs
Host bus clock output at 2.5V.
Power pin for the CPUCLKs. 2.5V
Ground pin for the CPU/2 clocks.
2.5V clock outputs at 1/2 CPU frequency.
Power pin for the CPU/2 clocks. 2.5V
Ground pin for the IOAPIC outputs.
IOAPIC clocks at 2.5V. Synchronous with CPUCLKs.
Power pin for the IOAPIC outputs. 2.5V.
2