ICS9248-95 Datasheet, PDF (2/16 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for PENTIUM/ProTM

ICS9248 - 95
Pin Descriptions
PIN NUMBER PIN NAME
1
VDDREF
REF0
2
PCI_STOP#¹
3,9,16,22,
33,40,44
GND
4
X1
5
X2
6,14
VDDPCI
PCICLK_F
7
MODE^{1, 2}
FS3¹
8
PCICLK0
13, 12, 11, 10 PCICLK [4:1]
15
BUFFER IN
17
SDRAM11
18, 20, 21, 28, 29,
31, 32, 34, 35, 37,
38
19,30,36
23
24
25
26
27
39
SDRAM [10:0]
VDDSDR
SDATA
SCLK
24MHz
FS1^{1, 2}
48MHz
FS0^{1, 2}
VDD48
SDRAM_F
41
CLK_STOP#
42, 43, 45
46
47
48
CPUCLK [2:0]
CPUCLK_F
VDDCPU
REF1
FS2^{1, 2}
TYPE
PWR
OUT
IN
DESCRIPTION
Ref, XTAL power supply, nominal 3.3V
14.318 Mhz reference clock.This REF output is the STRONGER
buffer for ISA BUS loads
Halts PCICLK [4:1]clocks at logic 0 level, when input low (In
mobile mode, MODE=0)
PWR Ground
IN
OUT
PWR
OUT
IN
IN
OUT
OUT
IN
OUT
Crystal input, has internal load cap (36pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz.
Supply for PCICLK_F and PCICLK [4:0], nominal 3.3V
Free running PCI clock not affected by PCI_STOP# for power
management.
Pin 17, pin 2 function select pin, 1=Desktop Mode, 0=Mobile Mode.
Latched Input.
Frequency select pin. Latched Input.
PCI clock outputs. Syncheronous to CPU clocks with 1-4ns skew
(CPU early)
PCI clock outputs. Syncheronous to CPU clocks with 1-4ns skew
(CPU early)
Input to Fanout Buffers for SDRAM outputs.
SDRAM clock output Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset).
OUT
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset).
PWR
IN
IN
OUT
IN
OUT
IN
PWR
OUT
IN
OUT
OUT
PWR
OUT
IN
Supply for SDRAM [11:0] and CPU PLL Core, nominal 3.3V.
Data input for I²C serial input, 5V tolerant input
Clock input of I²C input, 5V tolerant input
24MHz output clock
Frequency select pin. Latched Input.
48MHz output clock
Frequency select pin. Latched Input
Power for 24 & 48MHz output buffers and fixed PLL core.
Free running SDRAM clock output. Not affected by CPU_STOP#
This asynchronous input halts CPUCLK & SDRAM (0:11) at logic
"0" level when driven low.
CPU clock outputs, powered by VDDCPU
Free running CPU clock. Not affected by the CPU_STOP#
Supply for CPU clocks, 3.3V nominal
14.318 MHz reference clock.
Frequency select pin. Latched Input
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
310D—04/12/05
2