ICS9159C-02 Datasheet, PDF (2/7 Pages) Integrated Circuit Systems – Frequency Generator and Integrated Buffer for PENTIUMTM

ICS9159C-02
Pin Configuration
28-Pin SOIC
Functionality
FS1 FS0
*VCO
X1, REF CPU
(MHz) (MHz)
0
0 118/17xX1 14.318 50(49.7)
0
1 65/7xX1 14.318 66.6(66.5)
1
0 92/11xX1 14.318 60(59.9)
1
1 Test mode TCLK TCLK/2
*VCO range is limited from 60 - 200 MHz
PCLK(0,3)
VCO/2
TCLK/2
BCLK(0,5)
PCLK/2
TCLK/4
DISK
24 MHz
TCLK/4
KEYBD
12 MHz
TCLK/8
Pin Descriptions
PIN NUMBER
1, 8, 14,
20, 26
2
3
4, 11, 17, 23
6, 7, 9, 10
13, 12
15, 16, 18 19,
21, 22
5
24
25
28, 27
PIN NAME
VDD
X1
X2
VSS
PCLK(0:3)
FS(0:1)
BCLK(0:5)
OEN
DISK
KEYBD
REF(0:1)
TYPE
PWR
IN
OUT
PWR
OUT
IN
OUT
IN
OUT
OUT
OUT
DESCRIPTION
Power for logic, PCLK and fixed frequency output buffers.
XTAL or external reference frequency input. This input includes
XTAL load capacitance and feedback bias for a 12 - 16 MHz
crystal, nominally 14.31818 MHz.
XTAL output which includes XTAL load capacitance.
Ground for logic, PCLK and fixed frequency output buffers.
Processor clock outputs which are a multiple of the input reference
frequency as shown in the table above.
Frequency multiplier select pins. See table above. These inputs have
internal pull-up devices.
Bus clock outputs are fixed at one half the PCLK frequency.
OEN tristates all outputs when low. This input has an internal pull-
up device.
The DISK controller clock is fixed at 24 MHz
(with 14.318 MHz input).
The KEYBD clock is fixed at 12 MHz (with 14.318 MHz input).
REF is a buffered copy of the crystal oscillator or reference input
clock nominally 14.31818 MHz.
Note: BCLK buffers cannot be supplied with 5 volts (pins 14 and 20) if CPU and fixed frequencies (pins 1, 8, and 26) are being
supplied with 3.3 volts
2