ICS9159-13 Datasheet, PDF (2/7 Pages) Integrated Circuit Systems – Frequency Generator and Integrated Buffer for PENTIUM

ICS9159-13
Pin Descriptions
PIN NUMBER PIN NAME
1, 8, 14, 20, 26 VDD
2
X1
3
X2
4, 11, 17, 23
6, 7, 9, 10,
24, 25
13, 12
GND
PCLK(0:3)
FS(0:1)
15, 16, 18, 19,
21, 22
BCLK(0:5)
5
OEN
28, 27
REF(0:1)
TYPE
PWR
IN
OUT
PWR
OUT
IN
OUT
IN
OUT
DESCRIPTION
Power for logic, CPU and fixed frequency output buffers.
XTAL or external reference frequency input. This input includes XTAL load
capacitance and feedback bias for a 12 - 16 MHz crystal, nominally 14.31818 MHz.
XTAL output which includes XTAL load capacitance.
Ground for logic, CPU and fixed frequency output buffers.
Processor clock outputs which are a multiple of the input reference frequency as
shown in the table above.
Frequency multiplier select pins. See table above. These inputs have internal pull-up
devices.
Bus clock outputs are fixed at one half the PCLK frequency.
OEN tristates all outputs when low. This input has an internal pull-up device.
REF is a buffered copy of the crystal oscillator or reference input clock,
nominally 14.31818 MHz.
2