ICS9159-12 Datasheet, PDF (2/5 Pages) Integrated Circuit Systems – Frequency Generator and Buffers for Mobile Pentium Systems

ICS9159-12
Pin Descriptions
PIN NUMBER PIN NAME
8, 25
VDD
1
X1
2
3
4
5
11, 23
X2
OEN
BPIN
BHIN
GND
6, 7, 9, 10 BH(0:3)
13, 12
FS(0:1)
14, 20
15, 16, 18 19,
21, 22
24
VDD
BP(0:5)
CPU
26
28, 27
24M
REF(0:1)
TYPE
PWR
IN
OUT
IN
IN
IN
PWR
OUT
IN
PWR
OUT
OUT
OUT
OUT
DESCRIPTION
Power for logic, CPU and fixed frequency output buffers.
XTAL or external reference frequency input. This input includes XTAL load
capacitance and feedback bias for a 10 - 30 MHz XTAL.
XTAL output which includes XTAL load capacitance.
OEN tristates all outputs when low. This input has an internal pull-up device.
Input to BPIN(0:5) buffers.
Input to BHIN(0:3) buffers.
Ground for logic, CPU and fixed frequency output buffers.
Buffered copies of the BHIN input, typically used to drive the PCI device clock
inputs at one half the CPU frequency.
Frequency multiplier select pins. See table below. These inputs have internal pull-up
devices.
Power for BCLK output buffers.
Buffered copies of the BPIN input, typically used to drive the host device clock
inputs at the CPU frequency. 17 VSS PWR Ground for BCLK output buffers.
The CPU output, which is a multiple of the input reference frequency as shown in
the table above. Duty cycle is 50/50±5% with a maximum frequency of 100 MHz.
The 24M clock is fixed at 24 MHz.
REF is a buffered copy of the crystal oscillator or reference input clock,
nominally 14.31818 MHz.
Note: BCLK buffers cannot be supplied with 5 volts (Pins 14 and 20) if CPU
and fixed frequencies (Pins 1, 8 and 26) are being supplied with 3 volts.
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