ICS9150-04 Datasheet, PDF (2/19 Pages) Integrated Circuit Systems – Pentium Pro™ and SDRAM Frequency Generator

ICS9150- 04
Pin Descriptions
PIN NUMBER
PIN NAME
IOAPIC2
2
CPU3.3#_2.5
3
REF0
4, 10, 17, 23, 31, 34,
40, 47, 53
GND
TYPE
DESCRIPTION
OUT IOAPIC clock output (14.318MHz) powered by VDDL1
Indicates whether VDDL1 & VDDL2 are 3.3 or 2.5V. Output
IN
buffer strength compensates for VDDL selection to maintain
CPU to SDRAM skew. High = 2.5V, Low = 3.3V. Has pull-up
to VDDL1, must use series resistor for 3.3 or 5V logic levels.
OUT 14.318 MHz reference clock outputs.
PWR Ground.
5
X1
IN 14.318MHz input. Has internal load cap, (nominal 33pF).
6
8
9
11, 12,
13, 14
27
28
X2
PCICLK_F
FS1¹
PCICLK0
FS2¹
PCICLK (1:4)
SDATA
SCLK
OUT
OUT
IN
OUT
IN
Crystal output. Has internal load cap (33pF) and feedback
resistor to X1
Free running BUS clock during PCI_STOP#=0.
Latched frequency select input. Has pull-up to VDD2.
BUS clock output
Latched frequency select input. Has pull-up to VDD2.
OUT BUS clock outputs.
IN Serial data in for serial config port. (I²C)
IN Clock input for serial config port. (I²C)
24MHz
30
FS0¹
OUT 24MHz clock output for Super I/O or FD.
IN Latched frequency select input. Has pull-up to VDD4.
48MHz
29
MODE¹
1, 7, 15, 20, 26, 37, VDD2, VDD1,
43
VDD3, VDD4
50, 56
VDDL2, VDDL1
18, 19, 21, 22, 24,
25, 32, 33, 35, 36, SDRAM (0:15)
38, 39, 41, 42, 44, 45
55
IOAPIC0
46, 48, 49, 51, 52 CPUCLK (0:4)
IOAPIC1
54
CPU_STOP#
PCICLK5
16
PCI_STOP#
OUT
IN
PWR
PWR
48MHz clock output for USB.
Latched input for MODE select. Converts 2 outputs to power
management CPU_STOP# and PCI_STOP# when low. Has pull-
up to VDD4.
Nominal 3.3V power supply, see power groups for function.
CPU and IOAPIC clock buffer power supply, either 2.5 or 3.3V
nominal.
OUT SDRAM clocks
OUT
OUT
OUT
IN
OUT
IN
IOAPIC clock output. (14.318 MHz) Poweredby VDDL1
CPU Output clocks. Powered by VDDL2 (60 or 66.6MHz)
IOAPIC clock output. (14.31818 MHz) Powered by VDDL1
Halts CPUCLK clocks at logic "0" level when low. (in mobile,
MODE=0)
PCI BUS clock 5
Halts PCICLK (0:4) at logic "0" level when low. (in mobile,
MODE=0)
Notes:
1: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
2