ICS9148-46 Datasheet, PDF (2/9 Pages) Integrated Circuit Systems – Pentium/ProTM System Clock Chip

ICS9148-46
Pin Descriptions
PIN NUMBER
1
2
3
4
5
6, 7, 9, 10
8
11
12
13
14
PIN NAME
GND1
X1
X2
GND2
PCICLK_F
PCICLK (0:3)
VDD2
VDD3
48MHz
24_48MHz
GND3
15
SEL100/66.6#
16
SCLK
17
SDATA
18
PD#
19
20
21
22
23, 24
25
26
27
28
CPU_STOP#
PCI_STOP#
GND
VDD
CPUCLK (1:0)
VDDL
REF1
VDD1
REF0
SEL 48#
TYPE
PWR
IN
OUT
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
IN
IN
IN
IN
IN
IN
PWR
PWR
OUT
PWR
OUT
PWR
OUT
IN
DESCRIPTION
Ground for REF (0:1), X1, X2.
XTAL_IN 14.318MHz Crystal input, has internal 33pF
load cap and feed back resistor from X2
XTAL_OUT Crystal output, has internal load cap 33pF
Ground for PCI outputs
Free Running PCI output. Not affected by PCI_STOP#
PCI clock outputs. TTL compatible 3.3V
Power for PCICLK outputs, nominally 3.3V
Poer for 48MHz
Fixed CLK output @ 48MHz
Fixed CLK output; 24MHz if pin 27 =1 at power up,
48MHz if pin 27=0 at power up.
Ground for 48MHz
Select pin for enabling 100MHz or 66.6MHz
H=100MHz, L=66.6MHz (PCI always synchronous
33.3MHz)
Clock input for I²C input
Data input for I²C input
Asynchronous input when driven active (LOW) disables
internal clocks, stops VCO early. All outputs are placed
in a LOW state at the end of the curent cycle.
Asynchronous input when driven active (LOW) stops
CPUCLK(0:1) in a LOW state.
Asynchronous input when driven active (LOW) stops
PCICLK(0:3) in a LOW state. PCICLK_F is not affected.
Ground for CPUCLK (0:1) and the core
Power for PLL core
CPU and Host clock outputs nominally 2.5V
Power for CPU outputs, nominally 2.5V
14.318MHz Reference clock output
Power for REF outputs.
14.318MHz clock output
Latched input at power up. When low, pin 13 is 48MHz.
2