ICS9148-18 Datasheet, PDF (2/11 Pages) Integrated Circuit Systems – Pentium/ProTM System Clock Chip

ICS9148-18
Pin Descriptions
PIN NUMBER
26
28
1
2
3, 12
4
5, 7, 8, 10, 11
6, 9
13, 21
14, 20
PIN NAME
REF0
GND1
X1
X2
GND2
PCICLK_F
PCICLK (0:4)
VDD2
VDD
GND
15
16
17
18
19
25
22
23, 24
27
SEL100/66.6#
FS0
PD#
CPU_STOP#
PCI_STOP#
VDDL
GNDL
CPUCLK (1:0)
VDD1
TYPE
OUT
PWR
IN
OUT
PWR
OUT
OUT
PWR
PWR
PWR
IN
IN
IN
IN
IN
PWR
PWR
OUT
PWR
DESCRIPTION
14.318MHz clock output
Ground for REF outputs
XTAL_IN 14.318MHz Crystal input, has internal 33pF load
cap and feed back resistor from X2
XTAL_OUT Crystal output, has internal load cap 33pF
Ground for PCI outputs
Free Running PCI output
PCI clock outputs. TTL compatible 3.3V
Power for PCICLK outputs, nominally 3.3V
Isolated power for core, nominally 3.3V
Isolated ground for core
Select pin for enabling 100MHz or 66.6MHz
H=100MHz, L=66.6MHz (PCI always synchronous 33.3MHz)
Frequency Select pin
Powers down chip, active low
Halts CPU clocks at logic "0" level when low
Halts PCI Bus at logic "0" level when low
Power for CPU outputs, nominally 2.5V
Ground for CPU outputs.
CPU and Host clock outputs @ 2.5V
Power for REF outputs.
Select Functions
(Functionality determined by FS0 and SEL100/66# pin, see below)
Functionality
Tristate
Testmode
CPUCLK
HI - Z
TCLK/2¹
PCI,
PCI_F
HI - Z
TCLK/6¹
REF0
HI - Z
TCLK¹
Notes:
1. TCLK is a test clock driven on the X1 (crystal in pin) input during test mode.
SEL 100/66# FS0
Function
0
0
Tri-State
0
-
(Reserved)
0
-
(Reserved)
0
1 Active 66.6MHz CPU, 33.3 PCI
1
0
Test Mode
1
-
(Reserved)
1
-
(Reserved)
1
1
Active 100MHz CPU, 33.3 PCI
2