ICS9147-09 Datasheet, PDF (2/9 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for 686 Series CPUs

ICS9147- 09
Pin Descriptions
PIN NUMBER
2
3, 9, 16, 22,
27, 33, 39, 45
4
5
41
8, 10, 11, 12, 14,
15
23
24
47
1, 6, 13, 19,
30, 36, 48
17, 18, 20, 21, 28,
29, 31, 32, 34,
35, 37, 38
40
PIN NAME
REF
FS1
GND
X1
X2
VDDL
BUS (1:5)
BUS6
FS0
CPU_STOP#
PD#
24M
BSEL
VDD3
SDRAM (1:12)
CPUH/AGP
42, 43
CPUL (1:2)
7, 25, 26
46
N/C
48M
FS2
44
IOAPIC
TYPE
OUT
IN
DESCRIPTION
Reference clock output*
Logic input frequency select Bit1*. Input latched at Poweron.
PWR Ground.
IN
OUT
PWR
OUT
OUT
IN
IN
IN
OUT
IN
PWR
Crystal input. Nominally 14.318 MHz. Has internal load cap
Crystal output. Has internal load cap and feedack resistor to X1
2.5 or 3.3V buffer power for CPUL and IOAPIC output buffers.
BUS clock outputs. see select table for frequency
BUS clock output. See select table for frequency.*
Logic input frequency select Bit0.*. Input latched at Poweron.
Halts CPU Clocks at Logic "0" level when low. Internal Pull-up
Powers down chip, active low. Internal Pull-up
24MHz fixed clock.*
Logic input* for selecting synchronous or asynchronous BUS
frequency- see table above. Input latched at Poweron.*
3.3 volt core logic and buffer power
OUT SDRAM clocks at CPU speed. See select table for frequency.
OUT
OUT
—
OUT
IN
OUT
CPU clock operates at SDRAM VDD level (3.3V nom), for AGP etc.
CPU clocks .See select table for frequency. Operates at down to
2.5V controlled by VDDL pin.
Pins not internally connected.
48 MHz fixed clock output*.
Logic input frequency select Bit 2*. Input latched at Poweron.
Reference clock (14.318MHz) powered by VDDL,
operating 2.5 to 3.3V.
* Bidirectional input/output pins, input logic level determined at internal power-on-reset are latched. Use 10Kohm resistor to
program logic Hi to VDD or GND for logic low.
2