ICS9112-26 Datasheet, PDF (2/4 Pages) Integrated Circuit Systems – Low Skew Output Buffer

ICS9112-26
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V_DD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics at 3.3V
T_A = 0 - 70C; Supply Voltage V_DD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
High-level Output Voltage
V_OH
V_DD = min to max, I_OH = -1 mA
V_DD = 3V, I_OH = -24 mA
V_DD = 3V, I_OH = 12 mA
Low-level Output Voltage
V_OL
V_DD = min to max, I_OH = 1 mA
V_DD = 3V, I_OH = 24 mA
V_DD = 3V, I_OH = 12 mA
High-level Input Current
I_OH
V_DD = 3V, V_O = 1V
V_DD = 3.3V, V_O = 1.65V
Low-level Input Current
I_OL
V_DD = 3V, V_O = 2V
V_DD = 3.3V, V_O = 1.65V
Input Current
I_I
Input Capacitance¹
C_I
Output Capacitance¹
CO
V = V_O or V_DD
V_DD = 3.3V, V_I = 0V or 3.3V
V_DD = 3.3V, V_I = 0V or 3.3V
Supply current
I_DD
REF = 0 MHz
Unloaded outputs at 66.67 MHz
1. Guaranteed by design, not 100% tested in production.
MIN TYP
V_DD - 0.2 3.3
2
2.9
2.4
3.1
0.0055
0.28
0.14
-61
-77
60
103
111
-5
3
3.2
22
25
MAX
0.2
0.8
0.55
-50
5
50
40
UNITS
V
V
V
V
V
V
µA
pF
pF
µA
mA
Switching Characteristics at 3.3V
T_A = 0 - 70C; Supply Voltage V_DD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
Low-to-high Propagation Delay¹
High-to-low Propagation Delay¹
Output Skew Window¹
Process Skew¹
t_PLH
t_PHL
T_sk(O)
T_sk(PR)
V_O = V_DD/2
V_O = V_DD/2
V_O = V_DD/2
V_O = V_DD/2
CLKIN High Time¹
T_high
66 MHz
133 MHz
CLKIN Low Time¹
T_low
Output Rise Slew Rate¹
T_r
Output Rise Slew Rate¹
T_f
66 MHz
133 MHz
0.3 to 0.6 V_DD
0.3 to 0.6 V_DD
1. Guaranteed by design, not 100% tested in production.
Notes:
1. Guaranteed by design and characterization. Not subject to 100% test.
2. CLK_IN input has a threshold voltage of 1.4V
3. All parameters expected with loaded outputs
MIN TYP MAX UNITS
4
5.6
7
ns
4
5.2
7
ns
50
100
ps
0.5
ps
6
ns
3
6
ns
3
2
3.6
5 V/ns
2
3.2
5 V/ns
2