ICS874003 Datasheet, PDF (2/12 Pages) Integrated Circuit Systems – PCI EXPRESS JITTER ATTENUATOR

Integrated
Circuit
Systems, Inc.
ICS874003
PCI EXPRESS
JITTER ATTENUATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 20
QA1, nQA1 Output
Differential output pair. LVDS interface levels.
2, 19
3, 4
5
6
7
V_DDO
QA0, nQA0
MR
BW_SEL
nc
Power
Output
Input
Input
Unused
Output supply pins.
Pulldown
Pullup/
Pulldown
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs (nQx) to go low and the inverted outputs
(Qx) to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS/LVTTL interface levels.
PLL Bandwidth input. See Table 3B.
No connect.
8
V_DDA
Power
Analog supply pin.
9
F_SELA
Input
Pulldown
Frequency select pin for QAx/nQAx outputs.
LVCMOS/LVTTL interface levels.
10
V_DD
Power
Core supply pin.
Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are
11
OEA
Input Pullup active. When LOW, the QAx/nQAx outputs are in a high impedance
state. LVCMOS/LVTTL interface levels.
12
CLK
Input Pulldown Non-inverting differential clock input.
13
nCLK
Input Pullup Inverting differential clock input.
14
GND
Power
Power supply ground.
Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are
15
OEB
Input Pullup active. When LOW, the QBx/nQBx outputs are in a high impedance
state. LVCMOS/LVTTL interface levels.
16
F_SELB
Input
Pulldown
Frequency select pin for QBx/nQBx outputs.
LVCMOS/LVTTL interface levels.
17, 18 nQB1, QB1 Output
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
TABLE 3A. OUTPUT ENABLE FUNCTION TABLE
Inputs
OEA
OEB
0
0
1
1
Outputs
QAx/nQAx QBx/nQBx
HiZ
HiZ
Enabled
Enabled
TABLE 3B. PLL BANDWIDTH/PLL BYPASS CONTROL
Inputs
PLL_BW
0
1
Float
PLL
Bandwidth
~200kHz
~800kHz
~400kHz
874003AG
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2
REV. A JANUARY 25, 2006