ICS874003 Datasheet, PDF (1/12 Pages) Integrated Circuit Systems – PCI EXPRESS JITTER ATTENUATOR

Integrated
Circuit
Systems, Inc.
ICS874003
PCI EXPRESS
JITTER ATTENUATOR
GENERAL DESCRIPTION
The ICS874003 is a high performance Dif-
ICS
ferential-to-LVDS Jitter Attenuator designed for
HiPerClockS™ _{use in PCI Express systems. In some PCI}
Express systems, such as those found in
desktop PCs, the PCI Express clocks are
generated from a low bandwidth, high phase noise PLL
frequency synthesizer. In these systems, a jitter attenuator
may be required to attenuate high frequency random and
deterministic jitter components from the PLL synthesizer
and from the system board. The ICS874003 has 3 PLL
bandwidth modes: 200kHz, 400kHz, and 800kHz. The
200kHz mode will provide maximum jitter attenuation, but
with higher PLL tracking skew and spread spectrum
modulation from the motherboard synthesizer may be
attenuated. The 400kHz provides an intermediate bandwidth
that can easily track triangular spread profiles, while
providing good jitter attenuation. The 800kHz bandwidth
provides the best tracking skew and will pass most spread
profiles, but the jitter attenuation will not be as good as the
lower bandwidth modes. Because some 2.5Gb serdes have
x20 multipliers while others have than x25 multipliers, the
ICS874003 can be set for 1:1 mode or 5/4 multiplication
mode (i.e. 100MHz input/125MHz output) using the FSEL pins.
The ICS874003 uses ICS 3^rd Generation FemtoClock^TM
PLL technology to achive the lowest possible phase noise.
The device is packaged in a 20 Lead TSSOP package,
making it ideal for use in space constrained applications
such as PCI Express add-in cards.
FEATURES
• Three Differential LVDS output pairs
• One Differential clock input
• CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Output frequency range: 98MHz - 160MHz
• Input frequency range: 98MHz - 128MHz
• VCO range: 490MHz - 640MHz
• Cycle-to-cycle jitter: 35ps (maximum)
• 3.3V operating supply
• Three bandwidth modes allow the system designer to
make jitter attenuation/tracking skew design trade-offs
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
PLL BANDWIDTH
BW_SEL
0 = PLL Bandwidth: ~200kHz
Float = PLL Bandwidth: ~400kHz (default)
1 = PLL Bandwidth: ~800kHz
BLOCK DIAGRAM
OEA ^Pullup
F_SELA ^Pulldown
BW_SEL ^Float
0 = ~200kHz
Float = ~400kHz
1 = ~800kHz
CLK ^Pulldown
nCLK ^Pullup
Phase
Detector
VCO
490 - 640MHz
F_SELB ^Pulldown
M = ÷5 (fixed)
F_SELA
0 ÷5 (default)
1 ÷4
F_SELB
0 ÷5 (default)
1 ÷4
QA0
nQA0
QA1
nQA1
QB0
nQB0
PIN ASSIGNMENT
QA1 _{1 20} nQA1
VDDO 2
1 9 VDDO
QA0 3 18 QB1
nQA0 4 17 nQB1
MR 5 16 F_SELB
BW_SEL 6 15 OEB
nc 7 14 GND
VDDA 8
13 nCLK
F_SELA 9 12 CLK
VDD 10 11 OEA
ICS874003
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
MR ^Pulldown
OEB ^Pullup
874003AG
www.icst.com/products/hiperclocks.html
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REV. A JANUARY 25, 2006