ICS8602 Datasheet, PDF (2/10 Pages) Integrated Circuit Systems – ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8602
ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL
CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
V_DDA
Power
Analog supply pin.
2
V_DD
Power
Core supply pin.
3
CLK
Input Pulldown Non-inverting differential clock input.
4
nCLK
Input Pullup Inverting differential clock input.
5, 8, 12 16,
18, 22, 25, 29
6, 7
9
10, 14, 20,
24, 27, 31
11, 13, 15, 19, 21,
23, 26, 28, 30
17
32
GND
Power
DIV_SEL0, DIV_SEL1 Input
FB_IN
Input
V_DDO
Q0, Q1, Q2, Q3, Q4,
Q5, Q6, Q7, Q8
Power
Output
MR/nOE
Input
PLL_SEL
Input
Power supply ground.
Pulldown
Pulldown
Determines output divider valued in Table 3.
LVCMOS / LVTTL interface levels.
Feedback input to phase detector for regenerating clocks
with "zero delay". LVCMOS / LVTTL interface levels.
Output supply pins.
Pulldown
Pullup
Clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Active HIGH Master Reset. Active LOW output enable.
When logic HIGH, the internal dividers are reset and
the outputs are tri-stated (HiZ). When logic LOW, the
internal dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
Selects between the PLL and the reference clock as
the input to the dividers. When HIGH, selects PLL.
When LOW, selects reference clock.
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLUP
R_PULLDOWN
C_PD
R_OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
Test Conditions
V_DD, V_DDA, V_DDO = 3.47V
Minimum
Typical
51
51
Maximum
4
Units
pF
KΩ
KΩ
TBD
pF
7
Ω
TABLE 3A. CONTROL INPUT FUNCTION TABLE, PLL_SEL = 1
DIV_SEL1 DIV_SEL0
0
0
fOUT = fIN
Frequency Range (MHz)
Minimum
Maximum
125
250
0
1
62.5
125
1
0
31.25
62.5
1
1
15.625
31.25
TABLE 3B. CONTROL INPUT FUNCTION TABLE, PLL_SEL = 0
PLL BYPASS MODE
DIV_SEL1 DIV_SEL0
Frequency Divider
fIN
fOUT
0
0
fIN
fIN/2
0
1
fIN
fIN/4
1
0
fIN
fIN/8
1
1
fIN
fIN/16
8602BY
www.icst.com/products/hiperclocks.html
2
REV. F APRIL 16, 2003