ICS85408 Datasheet, PDF (2/12 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

Integrated
Circuit
Systems, Inc.
ICS85408
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2
nQ6, Q6
Output
Differential output pair. LVDS interface levels.
3, 4
nQ5, Q5
Output
Differential output pair. LVDS interface levels.
5, 6
nQ4, Q4
Output
Differential output pair. LVDS interface levels.
7, 8
nQ3, Q3
Output
Differential output pair. LVDS interface levels.
9, 10
nQ2, Q2 Output
Differential output pair. LVDS interface levels.
11, 12
nQ1, Q1 Output
Differential output pair. LVDS interface levels.
13, 14
nQ0, Q0
Output
Differential output pair. LVDS interface levels.
15
nCLK
Input
Pullup Inverting differential clock input.
16
CLK
Input Pulldown Non-inverting differential clock input.
17, 19, 20
18, 21
V_DD
GND
Power
Power
Positive supply pins.
Power supply ground.
22
23, 24
OE
nQ7, Q7
Input
Output
Pullup
Output enable. Controls the enabling and disabling of outputs
Qx, nQx. When HIGH, the outputs are enabled. When LOW, the
outputs are in HiZ. LVCMOS / LVTTL interface levels.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C
IN
R_PULLUP
R_PULLDOWN
C_PD
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
4
pF
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
OE
0
1
Outputs
Q0:Q7 nQ0:nQ7
HiZ
HiZ
ACTIVE ACTIVE
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
CLK
nCLK
Outputs
Q0:Q7
nQ0:nQ7
Input to Output Mode
Polarity
0
1
LOW
HIGH
Differential to Differential
Non Inverting
1
0
HIGH
LOW
Differential to Differential
Non Inverting
0
Biased; NOTE 1
LOW
HIGH
Single Ended to Differential Non Inverting
1
Biased; NOTE 1
HIGH
LOW
Single Ended to Differential Non Inverting
Biased; NOTE 1
0
HIGH
LOW
Single Ended to Differential
Inverting
Biased; NOTE 1
1
LOW
HIGH
Single Ended to Differential
Inverting
NOTE 1: Please refer to the Application Information section "Wiring the Differential Input to Accept Single Ended Levels".
85408BG
www.icst.com/products/hiperclocks.html
REV. A APRIL 25, 2005
2