ICS85408 Datasheet, PDF (1/12 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

Integrated
Circuit
Systems, Inc.
ICS85408
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
GENERAL DESCRIPTION
The ICS85408 is a low skew, high performance
ICS
1-to-8 Differential-to-LVDS Clock Distribution
HiPerClockS™ _{Chip and a member of the HiPerClockS™}
family of High Performance Clock Solutions
from ICS. The ICS85408 CLK, nCLK pair can ac-
cept most differential input levels and translates them to 3.3V
LVDS output levels. Utilizing Low Voltage Differential
Signaling (LVDS), the ICS85408 provides a low power, low
noise, low skew, point-to-point solution for distributing LVDS
clock signals.
Guaranteed output and part-to-part skew specifications make
the ICS85408 ideal for those applications demanding well
defined performance and repeatability.
FEATURES
• 8 Differential LVDS outputs
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum output frequency: 700MHz
• Translates any differential input signal (LVPECL, LVHSTL,
SSTL, HCSL) to LVDS levels without external bias networks
• Translates any single-ended input signal to LVDS with
resistor bias on nCLK input
• Multiple output enable inputs for disabling unused outputs
in reduced fanout applications
• Output skew: 50ps (maximum)
• Part-to-part skew: 550ps (maximum)
• Propagation delay: 2.4ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Lead-Free package RoHS compliant
BLOCK DIAGRAM
OE
CLK
nCLK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
PIN ASSIGNMENT
nQ6 1
Q6 2
nQ5 3
Q5 4
nQ4 5
Q4 6
nQ3 7
Q3 8
nQ2 9
Q2 10
nQ1 11
Q1 12
24 Q7
23 nQ7
22 OE
21 GND
20 VDD
19 VDD
18 GND
17 VDD
16 CLK
15 nCLK
14 Q0
13 nQ0
ICS85408
24-Lead, 173-MIL TSSOP
4.4mm x 7.8mm x 0.92mm body package
G Package
Top View
85408BG
www.icst.com/products/hiperclocks.html
1
REV. A APRIL 25, 2005