ICS8535-01 Datasheet, PDF (2/12 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS8535-01
LOW SKEW, 1-TO-4
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
V_EE
Power
Negative supply pin. Connect to ground.
Synchronizing clock enable. When HIGH, clock outputs follow clock
2
CLK_EN
Input
Pullup input. When LOW, Q outputs are forced low, nQ outputs are forced high.
LVCMOS / LVTTL interface levels.
3
CLK_SEL
Input
Pulldown
Clock select input. When HIGH, selects CLK1 input.
When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels.
4
CLK0
Input Pulldown LVCMOS / LVTTL clock input.
6
CLK1
Input Pulldown LVCMOS / LVTTL clock input.
5, 7, 8, 9
nc
Unused
No connect.
10, 13, 18
11, 12
V_CC
nQ3, Q3
Power
Output
Positive supply pins. Conncect to 3.3V.
Differential output pair. LVPECL interface levels.
14, 15
nQ2, Q2 Output
Differential output pair. LVPECL interface levels.
16, 17
nQ1, Q1 Output
Differential output pair. LVPECL interface levels.
19, 20
nQ0, Q0 Output
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C
IN
R_PULLUP
R_PULLDOWN
Parameter
CLK0, CLK1
Input Capacitance _{CLK_EN,}
CLK_SEL
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum Typical Maximum Units
4
pF
4
pF
51
KΩ
51
KΩ
ICS8535AG-01
www.icst.com/products/hiperclocks.html
2
REV. B JULY 5, 2001