ICS8535-01 Datasheet, PDF (1/12 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS8535-01
LOW SKEW, 1-TO-4
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS8535-01 is a low skew, high performance
,&6
1-to-4 LVCMOS-to-3.3V LVPECL fanout buffer
HiPerClockS™ _{and a member of the HiPerClockS™ family of High}
Performance Clock Solutions from ICS. The
ICS8535-01 has two single ended clock inputs.
the single ended clock input accepts LVCMOS or LVTTL in-
put levels and translate them to 3.3V LVPECL levels. The
clock enable is internally synchronized to eliminate runt clock
pulses on the output during asynchronous assertion/
deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8535-01 ideal for those applications demand-
ing well defined performance and repeatability.
FEATURES
• 4 differential 3.3V LVPECL outputs
• Selectable CLK0 or CLK1 inputs for redundant
and multiple frequency fanout applications
• CLK0 or CLK1 can accept the following differential input
levels: LVCMOS or LVTTL
• Maximum output frequency up to 266MHz
• Translates LVCMOS and LVTTL levels to 3.3V
LVPECL levels
• Output skew: 30ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 1.9ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
CLK_EN
CLK0
0
CLK1
1
CLK_SEL
D
Q
LE
PIN ASSIGNMENT
VEE 1
20 Q0
CLK_EN 2 19 nQ0
CLK_SEL 3
18 VCC
CLK0 4 17 Q1
Q0
nc 5 16 nQ1
nQ0
CLK1 6 15 Q2
nc 7 14 nQ2
Q1
nQ1
nc 8
nc 9
13 VCC
12 Q3
Q2
VCC 10 11 nQ3
nQ2
ICS8535-01
Q3
20-Lead TSSOP
nQ3
4.4mm x 6.5mm x 0.92mm body package
G Package
Top View
ICS8535AG-01
www.icst.com/products/hiperclocks.html
1
REV. B JULY 5, 2001