ICS853054 Datasheet, PDF (2/15 Pages) Integrated Circuit Systems – 4:1, DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS853054
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
PCLK0
Input
Pulldown Non-inverting differential LVPECL clock input.
2
nPCLK0
Input
Pullup/Pulldown
Inverting differential LVPECL clock input.
V /2 default when left floating.
CC
3
PCLK1
Input
Pulldown Non-inverting differential LVPECL clock input.
4
5, 16
6, 7
nPCLK1
V_CC
SEL0, SEL1
Input
Power
Input
Pullup/Pulldown
Pulldown
Inverting differential LVPECL clock input.
V_CC/2 default when left floating.
Positive supply pins.
Clock select input pins. LVCMOS/LVTTL interface levels.
8, 13
9
V_EE
PCLK2
Power
Input
Pulldown
Negative supply pin.
Non-inverting differential LVPECL clock input.
10
nPCLK2
Input
Pullup/Pulldown
Inverting differential LVPECL clock input.
V_CC/2 default when left floating.
11
PCLK3
Input
Pulldown Non-inverting differential LVPECL clock input.
12
14, 15
nPCLK3
nQ, Q
Input
Output
Pullup/Pulldown
Inverting differential LVPECL clock input.
V_CC/2 default when left floating.
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
R_PULLDOWN
R_VDD/2
Parameter
Input Pulldown Resistor
Pullup/Pulldown Resistosr
Test Conditions
Minimum Typical
75
50
Maximum
Units
kΩ
kΩ
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs
SEL1 SEL0
0
0
0
1
1
0
1
1
Outputs
Q/nQ
PCLK0/nPCLK0
PCLK1/nPCLK1
PCLK2/nPCLK2
PCLK3/nPCLK3
853054AG
www.icst.com/products/hiperclocks.html
2
REV. A JANUARY 5, 2006