ICS85304-01 Datasheet, PDF (2/13 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS85304-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2
Q0, nQ0
Output
Differential output pair. LVPECL interface levels.
3, 4
Q1, nQ1 Output
Differential output pair. LVPECL interface levels.
5, 6
Q2, nQ2
Output
Differential output pair. LVPECL interface levels.
7, 8
Q3, nQ3
Output
Differential output pair. LVPECL interface levels.
9, 10
Q4, nQ4
Output
Differential output pair. LVPECL interface levels.
11, 18, 20
12
V_CC
CLK_SEL
Power
Input
Positive supply pins. Connect to 3.3V.
Clock select input. When HIGH, selects PCLK, nPCLK inputs.
Pulldown When LOW, selects CLK, nCLK inputs.
LVTTL / LVCMOS interface levels.
13
CLK
Input Pulldown Non-inverting differential clock input.
14
nCLK
Input Pullup Inverting differential clock input.
15
V_EE
Power
Negative supply pin. Connect to ground.
16
PCLK
Input Pulldown Non-inverting differential LVPECL clock input.
17
nPCLK
Input Pullup Inverting differential LVPECL clock input.
Synchronizing clock enable. When HIGH, clock outputs follow clock
19
CLK_EN
Input Pullup input. When LOW, Q outputs are forced low, nQ outputs are forced
high. LVTTL / LVCMOS interface levels.
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLUP
R_PULLDOWN
Parameter
CLK, nCLK
Input Capacitance ^{PCLK, nPCLK}
CLK_EN,
CLK_SEL
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
51
51
Maximum
4
4
Units
pF
pF
4
pF
KΩ
KΩ
85304AG-01
www.icst.com/products/hiperclocks.html
2
REV. B JULY 13, 2001