ICS85304-01 Datasheet, PDF (1/13 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS85304-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS85304-01 is a low skew, high perfor-
,&6
mance 1-to-5 Differential-to-3.3V LVPECL fanout
HiPerClockS™ _{buffer and a member of the HiPerClockS™ family}
of High Performance Clock Solutions from ICS.
The ICS85304-01 has two selectable clock in-
puts. The CLK, nCLK pair can accept most standard differen-
tial input levels. The PCLK, nPCLK pair can accept LVPECL,
CML, or SSTL input levels. The clock enable is internally syn-
chronized to eliminate runt clock pulses on the outputs dur-
ing asynchronous assertion/deassertion of the clock enable
pin.
Guaranteed output and part-to-part skew characteristics
make the ICS85304-01 ideal for those applications
demanding well defined performance and repeatability.
FEATURES
• 5 differential 3.3V LVPECL outputs
• Selectable CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency up to 650MHz
• Translates any single-ended input signal to 3.3V LVPECL
levels with resistor bias on nCLK input
• Output skew: 35ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 2.1ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
CLK_EN
CLK
nCLK
00
PCLK
nPCLK
11
CLK_SEL
D
Q
LE
PIN ASSIGNMENT
Q0 1
20 VCC
nQ0 2 19 _{CLK_EN}
Q1 3
18 VCC
nQ1 4
17 _nPCLK
Q0
Q2 5
16 _PCLK
nQ0
nQ2 6
15 _VEE
Q3 7 14 _nCLK
Q1
nQ1
nQ3 8
Q4 9
13 CLK
12 CLK_SEL
Q2
nQ4 10 11 _VCC
nQ2
ICS85304-01
Q3
nQ3
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm Package Body
Q4
G Package
nQ4
Top View
85304AG-01
www.icst.com/products/hiperclocks.html
1
REV. B JULY 13, 2001