ICS85301 Datasheet, PDF (2/19 Pages) Integrated Circuit Systems – 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER

Integrated
Circuit
Systems, Inc.
ICS85301
2:1
DIFFERENTIAL-TO-LVPECL MULTIPLEXER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
PCLK0 Input Pulldown Non-inverting differential LVPECL clock input.
2
nPCLK0
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. V_CC/2 default when left floating.
3
PCLK1 Input Pulldown Non-inverting differential LVPECL clock input.
4
5
7, 16
nPCLK1
V_BB
nc
Input
Output
Unused
Pullup/
Pulldown
Inverting differential LVPECL clock input. V_CC/2 default when left floating.
Bias voltage.
No connect.
Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs.
6
CLK_SEL Input Pulldown When LOW, selects PCLK0, nPCLK0 inputs.
LVCMOS / LVTTL interface levels.
8, 13
9, 12, 14, 15
10, 11
V_CC
V_EE
nQ, Q
Power
Power
Output
Positive supply pins.
Negative supply pins.
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
1
37
37
Maximum
Units
pF
kΩ
kΩ
TABLE 3. CONTROL INPUT FUNCTION TABLE
Input
CLK_SEL
0
1
Input Selected
PCLK
PCLK0, nPCLK0
PCLK1, nPCLK1
85301AK
www.icst.com/products/hiperclocks.html
2
REV. A JANUARY 16, 2006