ICS853006 Datasheet, PDF (2/16 Pages) Integrated Circuit Systems – DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS853006
LOW SKEW, 1-TO-6
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 8, 13, 20
2, 3
V_CC
nQ0, Q0
Power
Output
Positive supply pins.
Differential output pair. LVPECL interface levels.
4, 5
nQ1, Q1 Output
Differential output pair. LVPECL interface levels.
6, 7
nQ2, Q2 Output
Differential output pair. LVPECL interface levels.
9
PCLK
Input Pulldown Non-inverting differential LVPECL clock input.
10
11
12
14, 15
nPCLK
V_BB
V_EE
nQ3, Q3
Input
Output
Power
Output
Pullup/
Pulldown
Inverting differential LVPECL clock input. V_CC/2 default when left floating.
Bias voltage.
Negative supply pin.
Differential output pair. LVPECL interface levels.
16, 17
nQ4, Q4 Output
Differential output pair. LVPECL interface levels.
18, 19
nQ5, Q5 Output
Differential output pair. LVPECL interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
R_PULLDOWN
R_VCC/2
Parameter
Input Pulldown Resistor
Input Pullup/Pulldown Resistor
Test Conditions
Minimum
Typical
75
50
Maximum
Units
KΩ
KΩ
TABLE 3. CLOCK INPUT FUNCTION TABLE
PCLK
Input
nPCLK
Outputs
Q0:Q5
nQ0:nQ5
Input to Output Mode
Polarity
0
1
LOW
HIGH
Differential to Differential
Non Inverting
1
0
HIGH
LOW
Differential to Differential
Non Inverting
0
Biased; NOTE 1
LOW
HIGH
Single Ended to Differential
Non Inverting
1
Biased; NOTE 1
HIGH
LOW
Single Ended to Differential
Non Inverting
Biased; NOTE 1
0
HIGH
LOW
Single Ended to Differential
Inverting
Biased; NOTE 1
1
LOW
HIGH
Single Ended to Differential
Inverting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
853006AG
www.icst.com/products/hiperclocks.html
2
REV. A AUGUST 18, 2004