ICS8523I-03 Datasheet, PDF (2/15 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS8523I-03
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
GND
Power
Power supply ground.
Synchronizing clock enable. When HIGH, clock outputs follow clock
2
CLK_EN
Input
Pullup input. When LOW, Q outputs are forced low, nQ outputs are forced
high. LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects differential CLK1, nCLK1
3
CLK_SEL
Input Pulldown inputs. When LOW, selects CLK0, nCLK0 inputs.
LVCMOS / LVTTL interface levels.
4
CLK0
Input Pulldown Non-inverting differential clock input.
5
nCLK0
Input
Pullup Inverting differential clock input.
6
CLK1
Input Pulldown Non-inverting differential clock input.
7
nCLK1
Input
Pullup Inverting differential clock input.
8, 9
nc
Unused
No connect.
10
11, 12
V
DD
nQ3, Q3
Power
Output
Core supply pin.
Differential output pair. LVHSTL interface levels.
13, 18
14, 15
V_DDO
nQ2, Q2
Power
Output
Output supply pins.
Differential output pair. LVHSTL interface levels.
16, 17
nQ1, Q1
Output
Differential output pair. LVHSTL interface levels.
19, 20
nQ0, Q0
Output
Differential output pair. LVHSTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R
PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
51
51
Maximum
4
Units
pF
KΩ
KΩ
8523AGI-03
www.icst.com/products/hiperclocks.html
2
REV. A OCTOBER 5, 2004