ICS8523I-03 Datasheet, PDF (1/15 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS8523I-03
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
GENERAL DESCRIPTION
ICS
The ICS8523I-03 is a low skew, high perfor-
mance 1-to-4 Differential-to-LVHSTL fanout buffer
HiPerClockS™ _{and a member of the HiPerClockS™ family of High}
Performance Clock Solutions from ICS. The
ICS8523I-03 has two selectable clock inputs.
The input pairs can accept most standard differential input
levels. The clock enable is internally synchronized to
eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8523I-03 ideal for those applications demand-
ing well defined performance and repeatability.
FEATURES
• 4 differential LVHSTL compatible outputs
• Selectable differential CLK0, nCLK0 and CLK1, nCLK1
clock inputs
• Clock input pairs can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum output frequency: 650MHz
• Translates any single-ended input signal to LVHSTL
levels with resistor bias on nCLK input
• Output skew: 50ps (maximum)
• Part-to-part skew: 400ps (maximum)
• Propagation delay: 1.2ns (typical)
• V_OH = 1V (maximum)
• 3.3V core, 1.8V output operating supply
• Lead-Free package available
• -40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
CLK_EN
CLK0
nCLK0
0
CLK1
nCLK1
1
CLK_SEL
D
Q
LE
PIN ASSIGNMENT
GND 1 20 Q0
CLK_EN 2 19 nQ0
CLK_SEL ³
1 8 _VDDO
CLK0 4 ¹⁷ Q1
Q0
nCLK0 5 16 nQ1
nQ0
CLK1 ^{6 15} Q2
Q1
nQ1
nCLK1 7
nc 8
nc ⁹
14 _nQ2
1 3 _VDDO
12 _Q3
Q2
VDD 10 ¹¹ nQ3
nQ2
ICS8523I-03
Q3
20-Lead TSSOP
nQ3
6.5mm x 4.4mm x 0.92mm body package
G Package
Top View
8523AGI-03
www.icst.com/products/hiperclocks.html
1
REV. A OCTOBER 5, 2004