ICS8521I Datasheet, PDF (2/14 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8521I
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
V_DD
Power
Power supply pin.
2
CLK
Input
Pulldown Non-inverting differential clock input.
3
nCLK
Input
Pullup Inverting differential clock input.
4
CLK_SEL
Input
Pulldown
Clock select input. When HIGH, selects PCLK, nPCLK inputs.
When LOW, selects CLK, nCLK. LVTTL / LVCMOS interface levels.
5
PCLK
Input
Pulldown Non-inverting differential LVPECL clock input.
6
nPCLK
Input
Pullup Inverting differential LVPECL clock input.
7
GND
Power
Power supply ground.
8
9, 16, 17,
24, 25, 32
CLK_EN
V
DDO
Input
Power
Pullup
Synchronizing clock enable. When HIGH, clock outputs follow
clock input. When LOW, Q outputs are forced low, nQ outputs
are forced high. LVCMOS /LVTTL interface levels.
Output supply pins.
10, 11
nQ8, Q8
Output
Differential output pair. HSTL interface levels.
12, 13
nQ7, Q7
Output
Differential output pair. HSTL interface levels.
14, 15
nQ6, Q6
Output
Differential output pair. HSTL interface levels.
18, 19
nQ5, Q5
Output
Differential output pair. HSTL interface levels.
20, 21
nQ4, Q4
Output
Differential output pair. HSTL interface levels.
22, 23
nQ3 Q3
Output
Differential output pair. HSTL interface levels.
26, 27
nQ2, Q2
Output
Differential output pair. HSTL interface levels.
28, 29
nQ1, Q1
Output
Differential output pair. HSTL interface levels.
30, 31
nQ0, Q0
Output
Differential output pair. HSTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
8521BYI
www.icst.com/products/hiperclocks.html
2
REV. A NOVEMBER 17, 2005