ICS85210-31 Datasheet, PDF (2/14 Pages) Integrated Circuit Systems – LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS85210-31
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
V_DD
Power
Core supply pin.
2
CLK0_EN
Pullup Pullup Synchronizing clock enable.
3
CLK0
Input Pulldown Non-inverting differential clock input.
4
nCLK0
Input
Pullup Inverting differential clock input.
5
CLK1_EN
Pullup Pullup Synchronizing clock enable.
6
CLK1
Input Pulldown Non-inverting differential clock input.
7
nCLK1
Input
Pullup Inverting differential clock input.
8
GND
Power
Power supply ground.
9, 16,
25, 32
V_DDO
Power
Output supply pins.
10, 11 nQB4, QB4 Output
Differential output pair. HSTL interface levels.
12, 13
nQB3, QB3 Output
Differential output pair. HSTL interface levels.
14, 15
nQB2, QB2 Output
Differential output pair. HSTL interface levels.
17, 18
nQB1, QB1 Output
Differential output pair. HSTL interface levels.
19, 20
nQB0, QB0 Output
Differential output pair. HSTL interface levels.
21, 22
nQA4, QA4 Output
Differential output pair. HSTL interface levels.
23, 24
nQA3, QA3 Output
Differential output pair. HSTL interface levels.
26, 27
nQA2, QA2 Output
Differential output pair. HSTL interface levels.
28, 29
nQA1, QA1 Output
Differential output pair. HSTL interface levels.
30, 31
nQA0, QA0 Output
Differential output pair. HSTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R
PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
85210AY-31
www.icst.com/products/hiperclocks.html
2
REV. B MARCH 19, 2004