ICS85210-31 Datasheet, PDF (1/14 Pages) Integrated Circuit Systems – LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS85210-31
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS85210-31 is a low skew, high perfor-
ICS
mance dual 1-to-5 Differential-to-HSTL Fanout
HiPerClockS™ _{Buffer and a member of the HiPerClockS™}
family of High Performance Clock Solutions
from ICS. The CLKx, nCLKx pairs can accept
most standard differential input levels. The ICS85210-31 is
characterized to operate from a 3.3V power supply.
Guaranteed output and part-to-part skew characteris-
tics make the ICS85210-31 ideal for those clock distri-
bution applications demanding well defined perfor-
mance and repeatability.
FEATURES
• Dual 1-to-5 HSTL compatible bank outputs
• 2 selectable differential clock input pairs
• CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, HSTL, SSTL, HCSL
• Maximum output frequency: 650MHz
• Translates any single ended input signal to
LVHSTL levels with resistor bias on nCLKx inputs
• Output skew: 50ps (maximum)
• Part-to-part skew: 350ps (maximum)
• Propagation delay: 2ns (maximum)
• 3.3V core, 1.8V output operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
CLK0
nCLK0
CLK0_EN
D
Q
LE
CLK1
nCLK1
CLK1_EN
D
Q
LE
85210AY-31
QA0
nQA0
QA1
nQA1
QA2
nQA2
QA3
nQA3
QA4
nQA4
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
QB4
nQB4
PIN ASSIGNMENT
VDD
CLK0_EN
CLK0
nCLK0
CLK1_EN
CLK1
nCLK1
GND
32 31 30 29 28 27 26 25
1
24
2
23
3
22
4 _ICS85210-31 21
5
20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
QA3
nQA3
QA4
nQA4
QB0
nQB0
QB1
nQB1
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
www.icst.com/products/hiperclocks.html
1
REV. B MARCH 19, 2004