ICS84330C Datasheet, PDF (2/19 Pages) Integrated Circuit Systems – 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
ICS84330C
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes op-
eration using a 16MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 6, NOTE 1.
The ICS84330C features a fully integrated PLL and therefore
requires no external components for setting the loop band-
width. A quartz crystal is used as the input to the on-chip
oscillator. The output of the oscillator is divided by 16 prior to
the phase detector. With a 16MHz crystal this provides a 1MHz
reference frequency. The VCO of the PLL operates over a
range of 250MHz to 700MHz. The output of the M divider is
also applied to the phase detector.
The phase detector and the M divider force the VCO output fre-
quency to be 2M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the LVPECL
output buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS84330C support two in-
put modes to program the M divider and N output divider. The
two input operational modes are parallel and serial. Figure 1
shows the timing diagram for each mode. In parallel mode the
nP_LOAD input is LOW. The data on inputs M0 through M8 and
N0 through N1 is passed directly to the M divider and N output
divider. On the LOW-to-HIGH transition of the nP_LOAD input,
the data is latched and the M divider remains loaded until the
next LOW transition on nP_LOAD or until a serial event occurs.
The TEST output is Mode 000 (shift register out) when operat-
ing in the parallel input mode. The relationship between the VCO
frequency, the crystal frequency and the M divider is defined as
follows:
fVCO
=
fxtal
16
x
2M
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock are
defined as 125 ≤ M ≤ 350. The frequency out is defined as
follows:
fout
=
fVCO
N
=
fxtal
16
x
2M
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider when S_LOAD tran-
sitions from LOW-to-HIGH. The M divide and N output divide
values are latched on the HIGH-to-LOW transition of S_LOAD.
If S_LOAD is held HIGH, data at the S_DATA input is passed
directly to the M divider on each rising edge of S_CLOCK.
The serial mode can be used to program the M and N bits and
test bits T2:T0. The internal registers T2:T0 determine the state
of the TEST output as follows in the table below:
S_CLOCK
T2 T1 T0
TEST Output
fOUT
0
00
Shift Register Out
fOUT
0
01
High
0
10
PLL Reference Xtal ÷ 16
0
11
(VCO ÷ M) /2 (non 50% Duty Cycle M divider)
1
00
fOUT
LVCMOS Output Frequency < 200MHz
fOUT
fOUT
fOUT
fOUT
1
01
Low
fOUT
1
1 0 (S_CLOCK ÷ M) /2 (non 50% Duty Cycle M divider) S_CLOCK ÷ N divider
1
11
fOUT ÷ 4
fOUT
SERIAL LOADING
S _ D ATA
S_LOAD
T2 T1 T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0
tt
SH
nP_LOAD
t
S
PARALLEL LOADING
M0:M8, N0:N1
M, N
nP_LOAD
84330CV
tt
SH
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
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2
REV. B DECEMBER 7, 2004