ICS83056I Datasheet, PDF (2/13 Pages) Integrated Circuit Systems – 6:1, SINGLE-ENDED MULTIPLEXER

Integrated
Circuit
Systems, Inc.
ICS83056I
6:1, SINGLE-ENDED MULTIPLEXER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
Q
Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
2, 4
nc
Unused
No connect.
6, 8,
9, 11,
13, 15
3
CLK5, CLK4,
CLK3, CLK2,
CLK1, CLK0
OE
Input Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels.
Input
Pullup
Output enable. When LOW, outputs are in HIGH impedance state.
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
5
7, 10,
14
GND
SEL2, SEL1,
SEL0
Power
Input
Power supply ground.
Pulldown
Clock select input. See Control Input Function Table.
LVCMOS / LVTTL interface levels.
12
V_DD
Power
Core and input supply pin.
16
V
Power
DDO
Output supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
C_PD
Power Dissipation Capacitance
(per output)
R_OUT
Output Impedance
Test Conditions
V_DDO = 3.465V
V_DDO = 2.625V
V = 1.89V
DDO
V_DDO = 3.465V
V_DDO = 2.625V
V_DDO = 1.89V
Minimum
Typical
4
51
51
18
20
30
7
7
10
Maximum
Units
pF
kΩ
kΩ
pF
pF
pF
Ω
Ω
Ω
TABLE 3. CONTROL INPUT FUNCTION TABLE
SEL2
0
0
0
0
1
1
1
1
Control Inputs
SEL1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
Input Selected to Q
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
LOW
LOW
83056AGI
www.icst.com/products/hiperclocks.html
2
REV. A JANUARY 18, 2006