ICS650-05 Datasheet, PDF (2/4 Pages) Integrated Circuit Systems – HDTV Clock Synthesizer

PRELIMINARY INFORMATION
ICS650-05
HDTV Clock Synthesizer
Pin Assignment
VDD 1
20 VDD
X2 2
19 OE
X1/ICLK 3
18 FRS
VDD 4
17 FRCLK
VDD 5
16 VDD
GND 6
15 GND
NC 7
14 GND
27M 8
13 54M
13.5M 9
12 27M
GND 10
11 GND
20 pin SSOP (QSOP)
FRCLK Output Select Table (in MHz)
FRS Pin 18
0
1
FRCLK Pin 17
74.175824
74.250000
Pin Descriptions
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
VDD
X2
X1/ICLK
VDD
VDD
GND
NC
27M
13.5M
GND
GND
27M
54M
GND
GND
VDD
FRCLK
FRS
OE
VDD
Type
P
XO
XI
P
P
P
-
O
O
P
P
O
O
P
P
P
O
I
I
P
Description
Connect to +3.3 V or +5.0 V. Must be same as other VDDs.
Crystal connection to a 27.0 MHz crystal or leave unconnected for clock input
Crystal connection. Connect to a 27.0 MHz fundamental mode crystal or clock input.
Connect to +3.3 V or +5.0 V. Must be same as other VDDs.
Connect to +3.3 V or +5.0 V. Must be same as other VDDs.
Connect to ground.
No Connect. Do not connect anything to this pin.
27 MHz buffered oscillator clock output.
13.5 MHz clock output.
Connect to ground.
Connect to ground.
27 MHz buffered clock output.
54 MHz buffered clock output.
Connect to ground.
Connect to ground.
Connect to +3.3 V or +5.0 V. Must be same as other VDDs.
Frame Rate Clock as shown on table.
Frame Rate Frequency Select input pin. Determines FRCLK output as shown on table.
Output Enable. Tri-states all clocks when low.
Connect to +3.3 V or +5.0 V. Must be same as other VDDs.
Key: I = Input with internal pull-up; O = output; P = power supply connection; XI, XO = crystal
connections
MDS 650-05 A
2
Revision 081199
Printed 12/4/00
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