ICS650-01 Datasheet, PDF (2/4 Pages) Integrated Circuit Systems – System Peripheral Clock Source

Pin Assignment
USEL 1
20 ^PSEL1
X2 ²
19 PSEL0
X1/ICLK ³
18 PCLK2
VDD ⁴
17 PCLK3
VDD 5
16 _VDD
GND 6
UCLK 7
15 _ASEL
14 _GND
20M 8
13 _14.318M
ACLK 9
12 PCLK1
PCLK4 ¹⁰
11 OE
20 pin (150 mil) SSOP
ICS650-01
System Peripheral Clock Source
Processor Clock (MHz)
PSEL1
0
0
0
M
M
M
1
1
1
PSEL0
0
M
1
0
M
1
0
M
PCLK1
25.00
TEST
TEST
40.00
33.3334
20.00
20.00
20.00
PCLK2,3
50.00
TEST
TEST
80.00
66.6667
40.00
33.3334
66.6667
PCLK4
18.75
TEST
TEST
20.00
25.00
25.00
25.00
25.00
1 Stops low all clocks except 20M
Audio Clock (MHz)
ASEL ACLK
0
49.152
M
24.576
1
12.288
USB Clock (MHz)
USEL
0
M
1
UCLK
12
24
48
0 = connect directly to ground, 1 = connect directly
to VDD, M=leave unconnected (floating)
Pin Descriptions
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
USEL
X2
X1/ICLK
VDD
VDD
GND
UCLK
20M
ACLK
PCLK4
OE
PCLK1
14.318M
GND
ASEL
VDD
PCLK3
PCLK2
PSEL0
PSEL1
Type
I
XO
XI
P
P
P
O
O
O
O
I
O
O
P
I
P
O
O
I
I
Description
UCLK Select pin. Determines frequency of USB clock per table above.
Crystal connection. Connect to parallel mode 14.31818 MHz crystal. Leave open for clock.
Crystal connection. Connect to parallel mode 14.31818 MHz crystal, or clock.
Connect to VDD. Must be same value as other VDD. Decouple with pin 6.
Connect to VDD. Must be same value as other VDD.
Connect to ground.
USB clock output per table above.
Fixed 20 MHz output for Ethernet. Only clock that runs when PSEL1=PSEL0=1.
AC97 Audio clock output per table above.
PCLK output number 4 per table above.
Output Enable. Tri-states all outputs when low.
PCLK output number 1 per table above.
14.31818 MHz buffered reference clock output.
Connect to ground.
ACLK Select pin. Determines frequency of Audio clock per table above.
Connect to VDD. Must be same value as other VDD. Decouple with pin 14.
PCLK output number 3 per table above.
PCLK output number 2 per table above.
Processor Select pin #0. Determines frequencies on PCLKs 1-4 per table above.
Processor Select pin #1. Determines frequencies on PCLKs 1-4 per table above.
Key: I = Input; XO/XI = crystal connections; O = output; P = power supply connection
MDS 650-01 C
2
Revision 092799
Printed 11/15/00
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