ICS558-01 Datasheet, PDF (2/5 Pages) Integrated Circuit Systems – PECL/CMOS TO CMOS CLOCK DIVIDER

ICS558-01
PECL/CMOS TO CMOS CLOCK DIVIDER
Pin Assignment
S0 1
S1 2
VDDP 3
PECLIN 4
PECLIN 5
GND 6
CMOSIN 7
OE0 8
16 SELPECL
15 VDDC
14 CLK1
13 CLK2
12 CLK3
11 CLK4
10 GND
9 OE1
16-pin 173 Mil (0.65mm) TSSOP
Pin Descriptions
Input Clock Selection
SELPECL
Input
0
CMOSIN
1
PECLIN
Tri-State Table
OE1
0
0
OE0
0
1
1
0
1
1
CLK 1
Tri-state
Clock ON
Tri-state
Clock ON
CLK 2, 3, 4
Tri-state
Tri-state
Clock ON
Clock ON
Output Divide Selection
S1 S0 Output Divide
0
0
/1
0
1
/2
1
0
/3
1
1
/4
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
S0
S1
VDDP
PECLIN
PECLIN
GND
CMOSIN
OE0
OE1
GND
CLK4
CLK3
CLK2
CLK1
VDDC
SELPECL
Pin Type
Input
Input
Power
Clock Input
Clock Input
Power
Clock Input
Input
Input
Power
Output
Output
Output
Output
Power
Input
Pin Description
Select 0 for output divider. See table above. Internal pull-up to VDDP.
Select 1 for output divider. See table above. Internal pull-up to VDDP.
Connect to +3.3 V or +5 V. Decouple to pin 6.
PECL input. Connect to ground if not used.
Complimentary PECL input. Connect to ground if not used.
Connect to ground.
CMOS input. Connect to ground if not used.
Output Enable 0. See table above. Internal pull-up to VDDP.
Output Enable 1. See table above. Internal pull-up to VDDP.
Connect to ground.
Low skew clock output.
Low skew clock output.
Low skew clock output.
Low skew clock output.
Connect to +2.5 V, +3.3 V, or +5 V. Decouple to pin 10.
Selects PECL or CMOS input. See table above. Internal pull-up to
VDDP.
MDS 558-01 C
2
Revision 122105
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