ICS551 Datasheet, PDF (2/4 Pages) Integrated Circuit Systems – 1 to 4 Clock Buffer

PRELIMINARY INFORMATION
ICS551
1 to 4 Clock Buffer
Pin Assignment
ICLK
Q1
Q2
Q3
1
8
2
7
3
6
4
5
8 pin SOIC
OE
VDD
GND
Q4
Pin Descriptions
Number
1
2
3
4
5
6
7
8
Name
ICLK
Q1
Q2
Q3
Q4
GND
VDD
OE
Type
CI
O
O
O
O
P
P
I
Description
Clock input. Internal pull-up resistor.
Clock Output 1.
Clock Output 2.
Clock Output 3.
Clock Output 4.
Connect to ground.
Connect to +3.3 V or +5.0 V.
Output Enable. Tri-states outputs when low. Internal pull-up resistor.
Key: CI = clock input, I = input, O = output, P = power supply connection
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of
0.01 µF should be connected between VDD on pin 7 and GND on pin 6, and a 33 Ω terminating resistor
may be used on each clock output if the trace is longer than 1 inch.
MDS 551 B
2
Revision 091200
Printed 11/14/00
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