ICS551 Datasheet, PDF (1/4 Pages) Integrated Circuit Systems – 1 to 4 Clock Buffer

PRELIMINARY INFORMATION
ICS551
1 to 4 Clock Buffer
Description
The ICS551 is a low cost, high speed single input
to four output clock buffer. Part of ICS’ Clock
Blocks^TM family, this is our lowest cost, small clock
buffer. See the ICS552-01B for a monolithic dual
version of the ICS551 in a 20 pin QSOP.
ICS makes many non-PLL and PLL based low
skew output devices, as well as Zero Delay Buffers
to synchronize clocks. Contact us for all of your
clocking needs.
Features
• Packaged in 8 pin SOIC
• Low cost clock buffer
• Low skew (250ps) outputs
• Input/output clock frequency up to 160 MHz
• Operating voltages of 3.0 to 5.5 V
• Non-inverting
• Ideal for networking clocks
• Output Enable mode tri-states outputs
• Full CMOS clock swings with 25mA drive
capability at TTL levels
• Advanced, low power CMOS process
Block Diagram
Q1
Q2
ICLK
Q3
Q4
Output Enable
MDS 551 B
1
Revision 091200
Printed 11/14/00
Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•[phone]tel•[phone]fax