9DBV0241 Datasheet, PDF (16/17 Pages) Integrated Circuit Systems – slew rate for each output

9DBV0241 DATASHEET
Ordering Information
Part / Order Number
9DBV0241AKLF
9DBV0241AKLFT
9DBV0241AKILF
9DBV0241AKILFT
Shipping Packaging
Tubes
Tape and Reel
Tubes
Tape and Reel
Package
24-pin VFQFPN
24-pin VFQFPN
24-pin VFQFPN
24-pin VFQFPN
Temperature
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“A” is the device revision designator (will not correlate with the datasheet revision).
Revision History
Rev.
A
B
C
Initiator Issue Date Description
Page #
RDW
8/13/2012
1. Updated electrical characteristics tables.
2. Move to final.
5-8
1. Changed VIH min. from 0.65*VDD to 0.75*VDD
2. Changed VIL max. from 0.35*VDD to 0.25*VDD
RDW 9/6/2014 ^{3. Added missing mid-level input voltage spec (VIM) of 0.4*VDD to}
0.6*VDD.
Various
4. Changed Shipping Packaging from "Trays" to Tubes".
5. Reformatted to new template
1. Updated front page text for family consistency
2. Updated block diagram for family consistency
3. Updated pin configuration to indicate that paddle is ground
4. Added epad as pin 25 to pin descritptions
5. Replaced "Driving LVDS" with "Alternate Terminations", adding
reference to AN-891.
1,2,4,5,
RDW 8/10/2015 6. Updated "Clock Input Parameters Table" correcting inconsistency with 6,7,8,
PCIe SIG specifications.
14
7. Widened allowable input frequency at each PLL mode frequency.
8. Updated phase jitter parameters with 12k-20M additive phase jitter and
added additive phase jitter graph.
9. Updated NLG24 package drawing with actual package info instead of
generic drawing.
2-OUTPUT 1.8V PCIE GEN1-2-3 ZERO DELAY / FANOUT BUFFER WITH ZO=100OHMS
16
REVISION C 08/11/15