ICS952004 Datasheet, PDF (12/19 Pages) Integrated Circuit Systems – Programmable Timing Control Hub™ for P4™ processor

Integrated
Circuit
Systems, Inc.
ICS952004
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = 0 - 70C; Supply Voltage V_DD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
Input High Voltage
V_IH
2
Input Low Voltage
V_IL
V_SS-0.3
Input High Current
Input Low Current
I_IH
V_IN = V_DD
-5
I_IL1
V_IN = 0 V; Inputs with no pull-up
-5
resistors
I_IL2
V_IN = 0 V; Inputs with pull-up
resistors
-200
MAX UNITS
V_DD+0.3 V
0.8
V
5
mA
mA
Operating Supply Current
I_DD3.3OP
C_L = Full load
215
280
mA
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance¹
Clk Stabilization^1,2
CPU to SDRAM SKEW
I_DD3.3PD
F_i
L_pin
C_IN
C_OUT
C_INX
T_STAB
IREF=2.32 mA
16
25
V_DD = 3.3 V
14.318
7
Logic Inputs
5
Output pin capacitance
6
X1 & X2 pins
27
45
From PowerUp or deassertion of
PowerDown to 1st clock.
1.3
1.8
0.4
1
mA
MHz
nH
pF
pF
pF
ms
ns
Delay¹
t_PZH,t_PZL
Output enable delay (all outputs)
1
t_PHZ,t_PLZ Output disable delay (all outputs) 1
10
ns
10
ns
1_{Guaranteed by design, not 100% tested in production.}
2_{See timing diagrams for buffered and un-buffered timing requirements.}
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