ICS952004 Datasheet, PDF (1/19 Pages) Integrated Circuit Systems – Programmable Timing Control Hub™ for P4™ processor

Integrated
Circuit
Systems, Inc.
ICS952004
Programmable Timing Control Hub™ for P4™ processor
Recommended Application:
SIS 645/650 style chipsets.
Output Features:
• 2 - Pairs of differential CPUCLKs (differential current mode)
• 1 - SDRAM @ 3.3V
• 8 - PCI @3.3V
• 2 - AGP @ 3.3V
• 2 - ZCLKs @ 3.3V
• 1- 48MHz, @3.3V fixed.
• 1- 24/48MHz, @3.3V selectable by I²C
(Default is 24MHz)
• 3- REF @3.3V, 14.318MHz.
Features/Benefits:
• Selectable asynchronous/synchronous AGP, ZCLK and
PCI outputs
• Programmable output frequency, divider ratios, output rise/
falltime, output skew.
• Programmable spread percentage for EMI control.
• Watchdog timer technology to reset system
if system malfunctions.
• Programmable watch dog safe frequency.
• Support I²C Index read/write and block read/write
operations.
• For PC133 SDRAM system use the ICS9179-16 as the
memory buffer.
• For DDR SDRAM system use the ICS93705 or
ICS93722 as the memory buffer.
• Uses external 14.318MHz crystal.
Pin Configuration
VDDREF 1
**FS0/REF0 2
**FS1/REF1 3
**FS2/REF2 4
GNDREF 5
X1 6
X2 7
GNDZ 8
ZCLK0 9
ZCLK1 10
VDDZ 11
*PCI_STOP# 12
VDDPCI 13
**FS3/PCICLK_F0 14
**FS4/PCICLK_F1 15
PCICLK0 16
PCICLK1 17
GNDPCI 18
VDDPCI 19
PCICLK2 20
PCICLK3 21
PCICLK4 22
PCICLK5 23
GNDPCI 24
48 VDDSD
47 SDRAM
46 GNDSD
45 CPU_STOP#*
44 CPUCLKT_1
43 CPUCLKC_1
42 VDDCPU
41 GNDCPU
40 CPUCLKT_0
39 CPUCLKC_0
38 IREF
37 GNDA
36 VDDA
35 SCLK
34 SDATA
33 PD#*/Vtt_PWRGD
32 GNDAGP
31 AGPCLK0
30 AGPCLK1
29 VDDAGP
28 VDDA48
27 48MHz
26 24_48MHz/MULTISEL*
25 GND48
48-Pin 300-mil SSOP
* These inputs have a 120K pull up to VDD.
** These inputs have a 120K pull down to GND.
Block Diagram
PLL2
X1
XTAL
X2
OSC
48MHz
/2
24_48MHz
REF (1:0)
2
Key Specifications:
• PCI - PCI output skew: < 500ps
• CPU - SDRAM output skew: < 1ns
PLL1
Spread
Spectrum
CPU
DIVDER
Stop
• AGP - AGP output skew: <150ps
Functionality
Control
ZCLK
DIVDER
Bit 2 Bit 7 Bit 6 Bit 5 Bit 4 CPU SDRAM ZCLK AGP
FS4 FS3 FS2 FS1 FS0 (MHz)
0 0 0 0 0 66.67
0 0 0 0 1 100.00
0 0 0 1 0 100.00
0 0 0 1 1 100.00
0 0 1 0 0 100.00
(MHz)
66.67
100.00
200.00
133.33
150.00
(MHz)
66.67
66.67
66.67
66.67
60.00
(MHz)
66.67
66.67
66.67
66.67
60.00
PCI
(MHz)
33.33
33.33
33.33
33.33
30.00
SDATA
SCLK
FS (4:0)
PD#
PCI_STOP#
CPU_STOP#
MULTISEL
PD#/Vtt_PWRGD
Logic
Config.
Reg.
PCI
DIVDER
Stop
AGP
DIVDER
SDRAM
DIVDER
0 0 1 0 1 100.00 125.00 62.50 62.50 31.25
0 0 1 1 0 100.00 160.00 66.67 66.67 33.33
0 0 1 1 1 100.00 133.33 80.00 66.67 33.33
0 1 0 0 0 100.00 200.00 66.67 66.67 33.33
0 1 0 0 1 100.00 166.67 62.50 62.50 31.25
0 1 0 1 0 100.00 166.67 71.43 83.33 41.67
Power Groups
0 1 0 1 1 80.00 133.33 66.67 66.67 33.33
VDDCPU = CPU
0 1 1 0 0 80.00 133.33 66.67 66.67 33.33
VDDPCI = PCICLK_F, PCICLK
0 1 1 0 1 95.00 95.00 63.33 63.33 31.67
VDDSD = SDRAM
0 1 1 1 0 95.00 126.67 63.33 63.33 31.67
AVDD48 = 48MHz, 24MHz, fixed PLL
0 1 1 1 1 66.67 66.67 50.00 50.00 25.00
AVDD = Analog Core PLL
Note: For additional margin testing frequencies, refer to Byte 4
VDDAGP= AGP
VDDREF = Xtal, REF
VDDZ = ZCLK
0489C—12/10/04
2 ^{CPUCLKT (1:0)}
2 ^{CPUCLKC (1:0)}
ZCLK (1:0)
2
6 ^{PCICLK (9:0)}
PCICLK_F (1:0)
2
AGP (1:0)
2
SDRAM
I REF