ICS950812 Datasheet, PDF (10/29 Pages) Integrated Circuit Systems – Frequency Generator with 200MHz Differential CPU Clocks

ICS950812
Table 3
PCI_STOP# I²C Control Table-Byte 0, Bit 3
PCI_STOP#
(Pin 34)
Byte 0 Bit 3
Write Bit
Byte 0, Bit 3 Read Bit
(Internal Status)
0
0
0
0
1
0
1
0
0
1
1
1`
Note: When this Byte 0, Bit 3 is low (0), all PCI clocks are stopped.
Table 4
CPUCLKT/C (2:0) Outputs I²C Control Table
CPU_STOP#
(Pin 53)
0
Byte 1
Bit 3, 4, 5
0
CPUCLKT/C (2:0) Outputs
Stop
0
1
Running
1
0
Running
1
1
Running
Note: Individual CPUCLK outputs are controlled by Byte 1, Bit 3, 4, and 5.
Table 5
PCICLK_F (2:0) Outputs I²C Control Table
PCI_STOP#
(Pin 34)
0
Byte 3
Bit 3, 4, 5
0
PCICLK (2:0) Outputs
Stop
0
1
Running
1
0
Running
1
1
Running
Note: Individual PCICLK outputs are controlled by Byte 3, Bit 3, 4, and 5.
Table 6
3V66 (5:2)/66MHz_OUT(2:0)/66MHz_IN I²C Control Table
CPU_STOP#
(Pin 53)
Byte 5
Bit 5
3V66 (5:2) (Driven)
66MHZ_OUT(2:0)/66MHZ_IN (Buffered)
0
0
Running
0
1
Stopped
1
0
Running
1
1
Running
Note: Activating Byte 5, Bit 5 will allow CPU_STOP# to control stop of pins 21, 22, 23, and 24.
0542G—08/21/03
10