ICS950410 Datasheet, PDF (10/15 Pages) Integrated Circuit Systems – AMD - K System Clock Chip

ICS950410
Advance Information
Absolute Maximum Rating
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS Notes
3.3V Core Supply Voltage
3.3V Logic Input Supply
Voltage
Storage Temperature
VDD_A
VDD_In
Ts
-
V_DD + 0.5V
V
1
-
GND - 0.5
V_DD + 0.5V
V
1
-
-65
150
°_C
1
Ambient Operating Temp Tambient
-
0
70
°C
1
Case Temperature
Tcase
-
115
°C
1
Input ESD protection HBM ESD prot
-
1_{Guaranteed by design and characterization, not 100% tested in production.}
2000
V
1
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP
MAX
UNITS Notes
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Low Threshold Input-
High Voltage
Low Threshold Input-
Low Voltage
Operating Supply Current
Operating Current
Powerdown Current
V_IH
V_IL
I_IH
I_IL1
I_IL2
V_{IH_FS}
V_{IL_FS}
I_DD3.3OP
I_DD3.3OP
I_DD3.3PD
3.3 V +/-5%
3.3 V +/-5%
V_IN = V_DD
V_IN = 0 V; Inputs with no pull-up
resistors
V_IN = 0 V; Inputs with pull-up
resistors
2
V_SS - 0.3
-5
-5
-200
3.3 V +/-5%
0.7
3.3 V +/-5%
Full Active, C_L = Full load;
all outputs driven
all diff pairs driven
all differential pairs tri-stated
V_SS - 0.3
V_DD + 0.3
V
1
0.8
V
1
5
uA
1
uA
1
uA
1
V_DD + 0.3
V
1
0.35
V
1
350
mA
1
400
mA
1
70
mA
1
12
mA
1
Input Frequency
Pin Inductance
Input Capacitance
Clk Stabilization
Modulation Frequency
Tdrive_PD#
Tfall_Pd#
F_i
V_DD = 3.3 V
14.31818
MHz
2
L_{pi n}
7
nH
1
C_IN
Logic Inputs
5
pF
1
C_OUT
Output pin capacitance
6
pF
1
C_INX
X1 & X2 pins
5
pF
1
T_STAB
From V_DD Power-Up or de-
assertion of PD# to 1st clock
1.8
ms
1
Triangular Modulation
30
33
kHz
1
CPU output enable after
PD# de-assertion
300
us
1
PD# fall time of
5
ns
1
Trise_Pd#
PD# rise time of
5
ns
1
SMBus Voltage
V_DD
2.7
Low-level Output Voltage
V_OL
@ I_PULLUP
Current sinking at
V_OL = 0.4 V
I_PULLUP
4
SCLK/SDATA
Clock/Data Rise Time
T_RI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
SCLK/SDATA
Clock/Data Fall Time
T_FI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
5.5
V
1
0.4
V
1
mA
1
1000
ns
1
300
ns
1
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.}
0888—04/06/04
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