ICS853058 Datasheet, PDF (10/15 Pages) Integrated Circuit Systems – 8:1, DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS853058
8:1, DIFFERENTIAL-TO-
3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER
SCHEMATIC EXAMPLE
An application schematic example of ICS853058 is shown in
Figure 5. The inputs can accept various types of differential sig-
nals. In this example, the inputs are driven by 3.3V LVPECL
drivers. The ICS853058 output is an LVPECL driver. An example
of LVPECL terminations is shown this schematic. Other termi-
nation approaches are available in the LVPECL Termination
Application Note. It is recommended at least one decoupling ca-
pacitor per power pin. The decoupling capacitor should be low
ESR and located as close as possible to the power pin.
Zo = 50
LVPECL
Zo = 50
Zo = 50
Zo = 50
LVPECL
R4
R5
50
50
3. 3V
R6
50
C1
0.1u
R1
R2
50
50
R3
50
U1
1
2
3
4
PCLK0
nPC LK0
PCLK1
5 ^nPCLK1
6 ^VCC
7
8
9
10
11
12
SEL0
SEL1
SEL2
PCLK2
nPC LK2
PCLK3
nPC LK3
I C S853058
PCLK7
nPCLK7
PCLK6
24
23
22
21
nPCLK6 ₂₀
VCC
Q0
nQ0
GND
PCLK5
nPCLK5
PCLK4
nPCLK4
19
18
17
16
15
14
13
Logic Control Input Examples
Set Logic
3.3V _{Input to}
'1'
RU1
1K
To Logic
Input
pins
RD1
Not Install
Set Logic
3.3V _{Input to}
'0'
RU2
Not Install
To Logic
Input
pins
RD2
1K
3.3V
Zo = 50
Zo = 50
C2
0.1u
R7
R8
50
50
+
-
LVPECL
R9
50
FIGURE 5. ICS853058 SCHEMATIC EXAMPLE
853058AG
www.icst.com/products/hiperclocks.html
10
REV. A APRIL 13, 2004