ICS9DB202 Datasheet, PDF (1/11 Pages) Integrated Circuit Systems – Two 0.7V current mode differential HCSL output pairs, 1 differential clock input

Integrated
Circuit
Systems, Inc.
ICS9DB202
PCI EXPRESS™
JITTER ATTENUATOR
GENERAL DESCRIPTION
The ICS9DB202 is a high perfromance 1-to-2 Dif-
ICS
ferential-to-HCSL Jitter Attenuator designed for use
HiPerClockS™ _{in PCI Express™ systems. In some PCI Express™}
systems, such as those found in desktop PCs, the
PCI Express™ clocks are generated from a low
bandwidth, high phase noise PLL frequency synthesizer. In these
systems, a jitter-attenuating device may be necessary in order
to reduce high frequency random and deterministic jitter com-
ponents from the PLL synthesizer and from the system board.
The ICS9DB202 has two PLL bandwidth modes. In low band-
width mode, the PLL loop bandwidth is 500kHz. This setting of-
fers the best jitter attenuation and is still high enough to pass a
triangular input spread spectrum profile. In high bandwidth mode,
the PLL bandwidth is at 1MHz and allows the PLL to pass more
spread spectrum modulation.
For serdes which have x10 reference multipliers instead of x12.5
multipliers, each of the two PCI Express™ outputs (PCIEX0:1)
can be set for 125MHz instead of 100MHz by configuring the
appropriate frequency select pins (FS0:1).
BLOCK DIAGRAM
IREF
+-
Current
Set
nOE0
1 HiZ
0 Enabled
nCLK
CLK
Phase
Detector
Loop
Filter
VCO
÷5
Internal Feedback
Features
• Two 0.7V current mode differential HCSL output pairs
• 1 differential clock input
• CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum output frequency: 140MHz
• Output skew: 110ps (maximum)
• Cycle-to-cycle jitter: 110ps (maximum)
• RMS phase jitter @ 100MHz, (1.5MHz - 22MHz):
2.42ps (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Lead-Free package available
• Industrial temperature information available upon request
PIN ASSIGNMENT
0
0 ÷4
1 ÷5
1
FS0
0
0 ÷5
1 ÷4
1
PLL_BW 1
2 0 VDDA
CLK 2 19 BYPASS
nCLK 3 18 IREF
FS0 4 17 FS1
VDD 5
16 VDD
GND 6 15 GND
PCIEXT0 7 14 PCIEXT1
PCIEXC0 8 13 PCIEXC1
VDD 9
12 VDD
nOE0 10 11 nOE1
ICS9DB202
20-Lead TSSOP
6.50mm x 4.40mm x 0.92
PCIEXT0
nPCIEXC0
package body
G Package
Top View
ICS9DB202
20-Lead, 209-MIL SSOP
5.30mm x 7.20mm x 1.75mm
body package
F Package
Top View
PCIEXT1
nPCIEXC1
BYPASS
nOE1
FS1
1 HiZ
0 Enabled
9DB202CG
www.icst.com/products/hiperclocks.html
1
REV. A OCTOBER 6, 2004